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Computational Aspects of Vlsi
01 Jan 1984-
About: The article was published on 1984-01-01 and is currently open access. It has received 862 citations till now. The article focuses on the topics: Very-large-scale integration.
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01 Jan 1985
TL;DR: This work recursively cuts the area of the chip into smaller and smaller regions until the routing problem within a region can be handled by the Dantzig-Wolfe decomposition method, and successively paste the adjacent regions together to obtain the routing of the whole chip.
Abstract: The circuit routing problem on a VLSI chip is an extremely large linear program with a very large number of rows and columns, too large to be solved even with the column-generating techniques. Based on the distribution of nets, we recursively cut the area of the chip into smaller and smaller regions until the routing problem within a region can be handled by the Dantzig-Wolfe decomposition method. Then we successively paste the adjacent regions together to obtain the routing of the whole chip.
53Â citations
TL;DR: The prefix sums algorithm is used in conjunction with broadcasting on short buses to obtain several efficient architectural designs for the following fundamental problems: 1) ranking linked lists, 2) counting the number of 1's in a sequence of n bits, and 3) sorting small sets.
Abstract: We propose to enhance traditional broadcast buses by the addition of a new feature that we call shift switching. We show that on a linear array of processors enhanced with shift switching, the prefix sums of n bits can be computed in [log(n+1)/log w] broadcasts, each over n switches, assuming a global bus of width w. Next our prefix sums algorithm is used in conjunction with broadcasting on short buses to obtain several efficient architectural designs for the following fundamental problems: 1) ranking linked lists, 2) counting the number of 1's in a sequence of n bits, and 3) sorting small sets. We see our main contribution in showing that the new bus feature leads to designs that are both theoretically interesting and practically relevant. >
53Â citations
01 May 1991
TL;DR: Asymptotically, the ACS-feedback no longer has to be processed recursively, i.e., there is no feedback and this fact can be exploited technically to design efficient and purely feedforward architectures for Viterbi decoding that have a modular extendable structure.
Abstract: The Viterbi-Algorithm (VA) is a common application of dynamic programming. The algorithm contains a nonlinear feedback loop (ACS-feedback, ACS: add-compare-select) which is the bottleneck in high data rate implementations. In this paper we show that, asymptotically, the ACS-feedback no longer has to be processed recursively, i.e., there is no feedback. With only negligible performance loss, this fact can be exploited technically to design efficient and purely feedforward architectures for Viterbi decoding that have a modular extendable structure. By designing one cascadable module, any speedup can be achieved simply by adding modules to the implementation. It is shown that optimization criteria, as minimum latency or maximum hardware efficiency, are met by very different architectures.
52Â citations
TL;DR: This paper proves that finding an optimal edge ranking of a graph is NP-hard, and shows that even finding a reasonably small edge ranking is infeasible in some cases.
51Â citations
TL;DR: In this paper, the authors gave improved approximations for two classical embedding problems: minimizing the number of crossings in a drawing on the plane of a bounded degree graph and minimizing the VLSI layout area of a graph of maximum degree four.
Abstract: We give improved approximations for two classical embedding problems: (i) minimizing the number of crossings in a drawing on the plane of a bounded degree graph; and (ii) minimizing the VLSI layout area of a graph of maximum degree four. These improved algorithms can be applied to improve a variety of VLSI layout problems. Our results are as follows. (i) We compute a drawing on the plane of a bounded degree graph in which the sum of the numbers of vertices and crossings is O(log3 n)$ times the optimal minimum sum. This is a logarithmic factor improvement relative to the best known result. (ii) We compute a VLSI layout of a graph of maximum degree four in a square grid whose area is O(log4 n)$ times the minimum layout area. This is an O(log2 n) improvement over the best known long-standing result.
50Â citations