In this paper we investigate the relationships between three different models of parallel computers based on mesh-connected arrays: the processor array (PA), which is an MIMD-array of independent processors, the instruction broadcasting array (IBA), where the instructions are broadcast to all the processors of a column and executed according to selector information which is broadcast to all the processors of a row, and the instruction systolic array (ISA), where the instructions are pumped through the array row by row and combined with selector information which is pumped through the array column by column. For every two of these models we determine tight bounds on the worst-case delay introduced by a transformation of a program on one model into an equivalent program on the other. The results show that the ISA concept combines the advantages of standard systolic arrays with those of the MIMD concept. Since in addition the ISA architecture has smaller area requirements than a corresponding systolic array or MIMD machine it is strong practical relevance.

Computational Aspects of Vlsi

The instruction systolic array and its relation to other models of parallel computers

The author studies a class of VLSI organizations with optical interconnects for fast solutions to several image processing tasks. The organization and operation of these architectures are based on a generic model called OMC, which is used to understand the computational limits in using free space optics in VLSI parallel processing systems. The relationships between OMC and shared memory models are discussed. Also, three physical implementations of OMC are presented. Using OMC, several parallel algorithms for fine grain image computing are presented. A set of processor efficient optimal O(log N) algorithms and a set of constant time algorithms are presented for finding geometric properties of digitized images. Finally, designs tailored to meet both the computation and communication needs of problems such as those involving irregular sparse matrices are examined. >

Parallel algorithms for image processing on OMC

It was conjectured by A Borodin et al that to solve the element distinctness problem requires TS= Omega (n/sup 2/) on a comparison-based branching program using space S and time T, which, if true, would be close to optimal since TS=O(n/sup 2/ log n) is achievable They showed recently (1987) that TS= Omega (n/sup 3/2/(log n)/sup 1/2/) The author shows a near-optimal tradeoff TS= Omega (n/sup 2- epsilon (n)/), where epsilon (n)=O(1/(log n)/sup 1/2/) >

Near-optimal time-space tradeoff for element distinctness

Thearea-time complexity of VLSI computations is constrained by the flow and the storage of information in the two-dimensional chip. We study here the information exchanged across the boundary of the cells of asquare-tessellation of the layout. When the information exchange is due to thefunctional dependence between variables respectively input and output on opposite sides of a cell boundary, lower bounds are obtained on theAT2 measure (which subsume bisection bounds as a special case). When information exchange is due to thestorage saturation of the tessellation cells, a new type of lower bound is obtained on theAT measure.

Area-time lower-bound techniques with applications to sorting

Highly parallel programs are often best understood in terms of logical patterns of inter process communication. In order to debug such programs, the user must determine the extent to which the intended patterns occur during execution. To facilitate this, we have designed and implemented a pattern-oriented debugger in which abstract, user-defined communication events can be described and animated. We report here on our initial experiences with its use.

Computational Aspects of Vlsi

Citations

The instruction systolic array and its relation to other models of parallel computers

Parallel algorithms for image processing on OMC

Near-optimal time-space tradeoff for element distinctness

Area-time lower-bound techniques with applications to sorting

Initial experiences with a pattern-oriented parallel debugger

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