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Computational Aspects of Vlsi
01 Jan 1984-
About: The article was published on 1984-01-01 and is currently open access. It has received 862 citations till now. The article focuses on the topics: Very-large-scale integration.
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TL;DR: A unified framework to reduce the upper bound on area for the straight-line drawing problems from O (n log n) (Crescenzi et al., 1992) to O ( n loglog n) .
Abstract: We investigate several straight-line drawing problems for bounded-degree trees in the integer grid without edge crossings under various types of drawings: (1) upward drawings whose edges are drawn as vertically monotone chains, a sequence of line segments, from a parent to its children, (2) order-preserving drawings which preserve the left-to-right order of the children of each vertex, and (3) orthogonal straight-line drawings in which each edge is represented as a single vertical or horizontal segment. Main contribution of this paper is a unified framework to reduce the upper bound on area for the straight-line drawing problems from O (n log n) (Crescenzi et al., 1992) to O (n loglog n) . This is the first solution of an open problem stated by Garg et al. (1993). We also show that any binary tree admits a small area drawing satisfying any given aspect ratio in the orthogonal straight-line drawing type. Our results are briefly summarized as follows. Let T be a bounded-degree tree with n vertices. Firstly, we show that T admits an upward straight-line drawing with area O (n loglog n) . If T is binary, we can obtain an O (n loglog n) -area upward orthogonal drawing in which each edge is drawn as a chain of at most two orthogonal segments and which has O (n/ log n) bends in total. Secondly, we present O (n loglog n) -area (respectively, -volume) orthogonal straight-line drawing algorithms for binary trees with arbitrary aspect ratios in 2-dimension (respectively, 3-dimension). Finally, we present some experimental results which shows the area requirements, in practice, for (order-preserving) upward drawing are much smaller than theoretical bounds obtained through analysis.
38 citations
17 Jan 2012
TL;DR: A data structure for submatrix maximum queries in Monge matrices or Monge partial matrices, where a query specifies a contiguous sub matrix of the given matrix, and its output is the maximum element of that submatrices.
Abstract: We describe a data structure for submatrix maximum queries in Monge matrices or Monge partial matrices, where a query specifies a contiguous submatrix of the given matrix, and its output is the maximum element of that submatrix. Our data structure for an n x n Monge matrix takes O(n log n) space, O(n log2n) preprocessing time, and can answer queries in O(log2n) time. For a Monge partial matrix the space bound and the preprocessing time both grow by the small factor α(n), where α(n) is the inverse Ackermann function. Our design exploits an interpretation of the column maxima in a Monge matrix (resp., Monge partial matrix) as an upper envelope of pseudo-lines (resp., pseudo-segments).We give two applications for this data structure: (1) For a set of n points in a rectangle B in the plane, we build a data structure that, given a query point p, returns the largest-area empty axis-parallel rectangle contained in B and containing p, in O(log4n) time. The preprocessing time is O(nα(n) log4n), and the space required is O(nα(n) log3n). This improves substantially a previous data structure of Augustine et al. [arXiv: 1004.0558] that requires quadratic space. (2) Given an n-node arbitrarily weighted planar digraph, with possibly negative edge weights, we build, in O(n log2n/log log n) time, a linear-size data structure that supports edge-weight updates and distance queries between arbitrary pairs of nodes (where the distance is minimum weight of a path in the graph between the pair of nodes), in O(n2/3 log5/3n) time for each update and query. This improves the O(n4/5 log13/5n)-time bound of Fakcharoenphol and Rao [JCSS 72, 2006]. Our data structure has already been applied in a recent maximum flow algorithm for planar graphs of Borradaile et al. [FOCS 2011], and we believe it will find additional applications.
38 citations
TL;DR: It is shown that, in size and depth, the circuit presented is of the same order as an optimal circuit implementing the PRAM, and it is reasonable to assume that CRCW PRAM instructions execute in constant time.
Abstract: A model of parallel computation called broadcasting with selective reduction (BSR) can be viewed as a concurrent-read concurrent-write (CRCW) parallel random access machine (PRAM) with one extension. An additional type of concurrent memory access is permitted in BSR, namely the BROADCAST instruction by means of which all N processors may gain access to all M memory locations simultaneously for the purpose of writing. At each memory location, a subset of the incoming broadcast data is selected and reduced to one value finally stored in that location. For several problems, BSR algorithms are known which require fewer steps than the corresponding best-known PRAM algorithms, using the same number of processors. A circuit is introduced to implement the BSR model, and it is shown that, in size and depth, the circuit presented is of the same order as an optimal circuit implementing the PRAM. Thus, if it is reasonable to assume that CRCW PRAM instructions execute in constant time, the assumption of a constant time BROADCAST instruction is no less reasonable. >
37 citations
01 Jan 1995
TL;DR: This paper shows how to construct a reduced quotient graph that satisfies the same temporal properties as the original graph and describes several methods for finding an invariant process whose correctness implies the correctness of the system.
Abstract: Model checking is a technique for determining whether a finite state-transition system satisfies a specification expressed in temporal logic. It has been used successfully to verify a number of highly complex circuit and protocol designs. A major hurdle in using this approach to verify realistic designs is the state explosion problem. This problem tends to occur when the number of state variables is very large. In this paper we discuss two techniques for handling this problem. The first technique is based on exploiting symmetry in the state-transition graph. We show how to construct a reduced quotient graph that satisfies the same temporal properties as the original graph. The second technique applies to systems that can have an arbitrary number of processes. In this case induction at the process level can be used to avoid the state explosion problem. An invariant process can frequently be found whose correctness implies the correctness of the system. We describe several methods for finding such an invariant process when one exists.
36 citations
01 Jan 1989
TL;DR: The term robustness is introduced and explained in detail with two examples, the SUPRENUM and the hypercube architecture, and it is shown that a simple mapping strategy (optimal clustering of the processes) gives almost as good results as the optimal mapping.
Abstract: Machines with distributed memory have the mapping problem—assigning processes to processors. In this paper we define the mapping problem as an optimization problem and discuss the question, how far is an optimum solution from an average or random solution. The term robustness is introduced and explained in detail with two examples, the SUPRENUM and the hypercube architecture. For the SUPRENUM architecture we show that a simple mapping strategy (optimal clustering of the processes) gives almost as good results as the optimal mapping. Optimal mapping is more important for the hypercube architecture. For nonhomogeneous networks adaptive routing seems promising.
36 citations