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Computational Aspects of Vlsi
01 Jan 1984-
About: The article was published on 1984-01-01 and is currently open access. It has received 862 citations till now. The article focuses on the topics: Very-large-scale integration.
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18 Sep 1997
TL;DR: This paper presents an algorithm which produces planar drawings of clustered graphs in a convention known as orthogonal grid rectangular cluster drawings and shows that the algorithm is optimal in terms of the number of bends in each edge.
Abstract: Clustered graphs are graphs with recursive clustering structures over the vertices. For graphical representation, the clustering structure is represented by a simple region that contains the drawing of all the vertices which belong to that cluster. In this paper, we present an algorithm which produces planar drawings of clustered graphs in a convention known as orthogonal grid rectangular cluster drawings. We present an algorithm which produces such drawings with On2 area and with at most 3 bends in each edge. This result is as good as existing results for classical planar graphs. Further, we show that our algorithm is optimal in terms of the number of bends in each edge.
31 citations
Cites background from "Computational Aspects of Vlsi"
...The orthogonal grid drawing convention appears in a number of applications, such as VLSI circuit design [27, 29, 47, 48] and diagrammatic interfaces for relational information systems [1, 42, 32, 35, 40]....
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TL;DR: In this paper, a parallel merging algorithm for an exclusive-read exclusive-write (EREW) parallel random access machine (PRAM) with k processors was presented, which merges two sorted lists of total length n in O(n/k+log n) time and constant extra space per processor.
Abstract: The authors present a parallel merging algorithm that, on an exclusive-read exclusive-write (EREW) parallel random-access machine (PRAM) with k processors merges two sorted lists of total length n in O(n/k+log n) time and constant extra space per processor, and hence is time-space optimal for any value of k >
31 citations
17 Jun 1991
TL;DR: This work states that the complete binary tree can be embedded into the square grid of the same size with almost optimal dilation (up to a very small factor).
Abstract: We consider several graph embedding problems which have applications in parallel and distributed computing and which have been unsolved so far. Our major result is that the complete binary tree can be embedded into the square grid of the same size with almost optimal dilation (up to a very small factor). To achieve this, we first state an embedding of the complete binary tree into the line with optimal dilation.
31 citations
21 Aug 2000
TL;DR: By designing VLSI layouts directly for an L-layer model, the layout area for a variety of networks can be reduced by a factor of about (L/2)/sup 2/ compared to the layouts area required under a 2-layer models, and the volume and maximum wire length can be reduction by about L/2, leading to considerably lower cost and/or higher performance.
Abstract: Current VLSI technology allows more than two wiring layers and the number is expected to rise in future. In this paper we show that, by designing VLSI layouts directly for an L-layer model, the layout area for a variety of networks can be reduced by a factor of about (L/2)/sup 2/ compared to the layout area required under a 2-layer model, and the volume and maximum wire length can be reduced by a factor of about L/2, leading to considerably lower cost and/or higher performance. The proposed layouts for k-ary n-cubes, hypercubes, butterfly networks, cube-connected cycles (CCC), folded hypercubes, generalized hypercubes, k-ary n-cube cluster-c, hierarchical hypercube networks, reduced hypercubes, hierarchical swap networks, and indirect swap networks, are the best layouts reported for these networks thus far and are optimal within a small constant factor under both the Thompson model and the multilayer grid model. All of our layouts are optimally scalable in that we can allow each network node to occupy the largest possible area (e.g., o(N/L/sup 2/) for hypercubes) without increasing the leading constant of the layout area, volume, or maximum wire length.
31 citations
Cites background from "Computational Aspects of Vlsi"
...…for an L-layer model, the layout area for a variety of networks can be reduced by a factor of about L 2 2 compared to the layout area required under a 2-layer model, and the volume and maximum wire length can be reduced by a factor of about L 2, leading to considerably lower cost and/or higher…...
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18 Sep 1996
TL;DR: In this article, an integer linear programming (ILP) formulation for the 2-level planarization problem is proposed. But the problem is NP-hard and it cannot be solved in polynomial time.
Abstract: A common method for drawing directed graphs is, as a first step, to partition the vertices into a set of k levels and then, as a second step, to permute the vertices within the levels such that the number of crossings is minimized. We suggest an alternative method for the second step, namely, removing the minimal number of edges such that the resulting graph is k-level planar. For the final diagram the removed edges are reinserted into a k-level planar drawing. Hence, instead of considering the k-level crossing minimization problem, we suggest solving the k-level planarization problem. In this paper we address the case k=2. First, we give a motivation for our approach. Then, we address the problem of extracting a 2-level planar subgraph of maximum weight in a given 2-level graph. This problem is NP-hard. Based on a characterization of 2-level planar graphs, we give an integer linear programming formulation for the 2-level planarization problem. Moreover, we define and investigate the polytope \(2\mathcal{L}\mathcal{P}\mathcal{S}\)(G) associated with the set of all 2-level planar subgraphs of a given 2-level graph G. We will see that this polytope has full dimension and that the inequalities occuring in the integer linear description are facet-defining for \(2\mathcal{L}\mathcal{P}\mathcal{S}\)(G). The inequalities in the integer linear programming formulation can be separated in polynomial time, hence they can be used efficiently in a cutting plane method for solving practical instances of the 2-level planarization problem. Furthermore, we derive new inequalities that substantially improve the quality of the obtained solution. We report on first computational results.
30 citations