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Computational Aspects of Vlsi
01 Jan 1984-
About: The article was published on 1984-01-01 and is currently open access. It has received 862 citations till now. The article focuses on the topics: Very-large-scale integration.
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TL;DR: The basic heuristic has been successfully applied to the problem of minimum-length Steiner routing and minimizing critical-sink Elmore delay and can be further improved to O(n log n) using sophisticated data structures.
22 citations
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08 Sep 2011TL;DR: A fundamentally new merging network for sorting numbers in a bit model is described, with new organizational approaches for optimal tuning of merging networks and the proper management of data flow.
Abstract: This work describes a large number of constructions for sorting N integers in the range [0, M - 1], for N ≤ M ≤ N2, for the standard VLSI bit model. Among other results, we attain:VLSI sorter constructions that are within a constant factor of optimal size, for all M and almost all running times T.a fundamentally new merging network for sorting numbers in a bit model.new organizational approaches for optimal tuning of merging networks and the proper management of data flow.
22 citations
Cites background or methods from "Computational Aspects of Vlsi"
...Minimum area bounds for sorters appear for special cases in [ 151 and [ 25 ]....
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...For T = fi, the area is just 0(N), the minimum possible area for sorting N numbers in the range 0 to N - 1 [ 25 ]....
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...More information about such a VLSI model can be found in [ 25 ]....
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TL;DR: Two algorithms which can recognize general context-free languages without restriction on the length of input string are proposed which essentially speed-up the dynamic programming procedure by using highly pipelining and parallelism of VLSI architecture.
22 citations
07 Nov 1993
TL;DR: A net-oriented method to analyze realistic faults to analyze the faults caused by a spot defect net by net, which shows that the method is much faster than other approaches published in literature.
Abstract: In this paper, a net-oriented method to analyze realistic faults is presented. The key point of the method is to analyze the faults caused by a spot defect net by net. First the possible faults related to a net are extracted. Hence all faults in a layout are extracted by enumerating all nets on the layout. An approach to calculate the critical area with respect to each fault is also described. A formula is proposed to compute the fault weight theoretically instead of weighting a fault by counting the number of appearances of the fault. The proposed method has been implemented on a HP750 workstation. To demonstrate its practical performance, all layouts in iscas85 benchmarks as well as some other layouts ranging from 450 to 28,000 transistors have been analyzed. The results show that our method is much faster than other approaches published in literature.
22 citations
23 Jul 2005
TL;DR: The search for flexibility in design without paying a significant area - time - power cost remains the primary problem for application specific and system on a chip (SoC) design.
Abstract: Application specific is always a tradeoff among competing design goals (or design parameters). In addition to the well established area (cost) - time (performance) - power metrics specific applications imply a relatively limited market so design cost becomes an especially important consideration. As technology offers increasing transistor density with lower cost power constraints limit frequency as the primary avenue to performance. The alternative is to use area (transistors) to recover performance putting an additional strain on the design budget. The search for flexibility in design without paying a significant area - time - power cost remains the primary problem for application specific and system on a chip (SoC) design.
22 citations