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Computational Aspects of Vlsi
01 Jan 1984-
About: The article was published on 1984-01-01 and is currently open access. It has received 862 citations till now. The article focuses on the topics: Very-large-scale integration.
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TL;DR: The technique can be used to transform a class of algorithms to specific forms that can be mapped directly onto higher-dimensional systolic networks, yet maintaining the same number of processing cells as its 1-D counterpart.
20Â citations
14 Apr 2004
TL;DR: A high-level discussion of the properties and potential advantages of the proposed massively parallel computers of the future that would be based on the fine-grained connectionist parallel models, rather than on either various multiprocessor architectures, or networked distributed systems, which are the two main architecture paradigms in building parallel computers in the late 20th and early 21st centuries.
Abstract: Models, architectures and languages for parallel computation have been of utmost research interest in computer science and engineering for several decades. A great variety of parallel computation models has been proposed and studied, and different parallel and distributed architectures designed as some possible ways of harnessing parallelism and improving performance of the general purpose computers.Massively parallel connectionist models such as artificial neural networks (ANNs) and cellular automata (CA) have been primarily studied in domain-specific contexts, namely, learning and complex dynamics, respectively. However, they can also be viewed as generic abstract models of massively parallel computers that are in many respects fundamentally different from the "main stream" parallel and distributed computation models.We compare and contrast herewith the parallel computers as they have been built by the engineers with those built by Nature. We subsequently venture onto a high-level discussion of the properties and potential advantages of the proposed massively parallel computers of the future that would be based on the fine-grained connectionist parallel models, rather than on either various multiprocessor architectures, or networked distributed systems, which are the two main architecture paradigms in building parallel computers of the late 20th and early 21st centuries. The comparisons and contrasts herein are focusing on the fundamental conceptual characteristics of various models rather than any particular engineering idiosyncrasies, and are carried out at both structural and functional levels. The fundamental distinctions between the fine-grain connectionist parallel models and their "classical" coarse-grain counterparts are discussed, and some important expected advantages of the hypothetical massively parallel computers based on the connectionist paradigms conjectured.We conclude with some brief remarks on the role that the paradigms, concepts, and design ideas originating from the connectionist models have already had in the existing parallel design, and what further role the connectionist models may have in the foreseeable future of parallel and distributed computing.
20Â citations
03 Jan 1989
TL;DR: A new model checking algorithm that can deal with conditional transitions is introduced and analyzed, and a theory is presented concerning the equivalence of finite state machines with respect to the preservation of temporal logic properties, which is used to develop a method to generalize between systems composed of differing numbers of similar finite state Machines.
Abstract: Finite state machines are common components of VLSI circuits. Because they occur so frequently, much effort has been spent building tools to assist in their design and verification. Since the proper sequencing of events is of paramount importance to the correct operation of a finite state machine, it is not surprising that temporal logics have been applied to the verification problem. These logics were originally developed by philosophers specifically for reasoning about the ordering of events in time. One of the first applications was the CTL model checking procedure developed by Clarke and Emerson, in which the truth of a formula of a branching-time temporal logic in a labelled state transition graph could be determined in time that was linear in both the size of the structure and the length of the formula. Although this algorithm has been shown to be very useful in the verification of several hardware controllers, it suffers from a number of serious drawbacks. These deficiencies include a notion of a finite state machine that does not permit external events to effect transitions, a lack of compositionality, and an inability to generalize between similar systems of different sizes. In this thesis, a number of alternative techniques are proposed to solve these problems. In particular, a new model checking algorithm that can deal with conditional transitions is introduced and analyzed. A theory is presented concerning the equivalence of finite state machines with respect to the preservation of temporal logic properties. Finally, this theory is used to develop a method to generalize between systems composed of differing numbers of similar finite state machines.
20Â citations
Cites background from "Computational Aspects of Vlsi"
...--see [Ullman 84] for a survey)have alreadybeen devised,most of these languages represent statemachines at a very low level....
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01 May 1990
TL;DR: It is shown that asymptotically, the ACS feedback no longer has to be processed recursively, i.e. there is no feedback, resulting in negligible performance loss.
Abstract: The Viterbi algorithm (VA) is a common application of dynamic programming. Since it contains a nonlinear ACS (add-compare-select) feedback loop, this loop is the bottleneck in high-data-rate implementations. It is shown that, asymptotically, the ACS feedback no longer has to be processed recursively, i.e. there is no feedback, resulting in negligible performance loss. This can be exploited to derive purely feedforward architectures for Viterbi decoding, so that a modular cascadable implementation results. By designing one cascadable module, any speedup can be achieved simply by adding modules to the implementation. It is shown that optimization criteria, e.g. minimum latency or maximum hardware efficiency, are met by very different architectures. >
20Â citations