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Computational Aspects of Vlsi

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The article was published on 1984-01-01 and is currently open access. It has received 862 citations till now. The article focuses on the topics: Very-large-scale integration.

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Proceedings ArticleDOI

A broadcast/reduce architecture for high-speed data compression

TL;DR: A parallel architecture for high-speed data compression based on textual substitution using a sliding window that combines a systolic array with trees for data broadcast and reduction and discusses layout issues arising from the tree interconnect.
Proceedings Article

Agreeing on a Leader in Real-Time.

TL;DR: Two protocols which solve the problem of maintaining the availability of a vital service in a real-time shared- memory multi-processor fault-tolerant computer system by tolerating the failure of any subset of the processors are given.
Proceedings ArticleDOI

Old and new algorithms for Toeplitz systems

TL;DR: This paper surveys some old, "well known" algorithms and some recent algorithms for solving Toeplitz linear systems and ToePLitz least squares problems and distinguishes between algorithms which require inner products and algorithms which avoid inner products, and thus are better suited to parallel implementation on some parallel architectures.
Proceedings ArticleDOI

A prototyping environment for control-oriented HW/SW systems using state-charts, activity-charts and FPGA's

TL;DR: A method for quickly designing and implementing HW/SW systems is described, based on the model of a flexible target architecture consisting of a dedicated controller that interacts with one or more pro cessing elements.
Journal ArticleDOI

The mesh with hybrid buses: an efficient parallel architecture for digital geometry

TL;DR: An efficient VLSI architecture obtained by augmenting the Mesh with Multiple Broadcasting with precharged 1-bit row and column buses is proposed and it is shown that the MHB is extremely well-suited for solving an entire slew of digital geometry tasks.