Book•
Computational Aspects of Vlsi
01 Jan 1984-
About: The article was published on 1984-01-01 and is currently open access. It has received 862 citations till now. The article focuses on the topics: Very-large-scale integration.
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TL;DR: This paper presents an improved Breakout Local Search for VSP (named BLS-RLE), a new parameter control mechanism that draws upon ideas from reinforcement learning theory to reach an interdependent decision on the number and on the type of perturbation moves.
17 citations
Cites background or methods from "Computational Aspects of Vlsi"
..., sizes, densities, applications) from the following benchmark sets: B1: The ISPD98 Circuit Benchmark Suite4 arising from VLSI design (one of the first applications of VSP [8, 2, 3])....
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...95, 1] and a value for l from the range [3, 150]....
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...It first arose in the context of Very Large Scale Integration (VLSI) design [2, 3], and has become popular in several other applications....
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...We further generate an additional set of 85 more challenging Barabási-Albert instances with 1000 ≤ |V| ≤ 2000, b = 2|V|/3, d ∈ [3, 100], and density in the range of [0....
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20 Oct 2014
TL;DR: This work proposes several scalable and high-speed FPGA-based implementations of a priority queue, including a Hybrid Priority Queue (H-PQ), which combines a register-based array with multiple BRAM-based trees, which provides, on average, very fast access times to the top items in the queue.
Abstract: Priority queues are abstract data structures where each element is associated with a priority, and the highest priority element is always retrieved first from the queue. The data structure is widely used within databases, including the last stage of a merge-sort, forecasting read-ahead I/O to stream data for the merge-sort, and replacement selection sort. Typical software implementations use a balanced binary tree-based structure, providing O(log N) time for both enqueue and dequeue operations.
17 citations
Cites background from "Computational Aspects of Vlsi"
...A more formal explanation that can be found in [7] states that when embedding a complete binary tree into a two-dimensional plane, the maximum distance between adjacent nodes (dilation) has a lower bound of Ω( √ N logN )....
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01 Jan 1996
TL;DR: The properties of arithmetic operations and their corresponding VLSI architectures with respect to the polar representation of the elements of Fermat prime fields are investigated and some new results regarding the applicability of the Fermat number transform when using the polar representations are presented.
Abstract: Theproperties of arithmetic operations in Fermat integer quotient ringsZ m , where m , are investigated. The arithmetic operations considered are mainly those involved in the computation of the Fermat number transform. We consider somewaysof representing the binary coded integers in such rings and investigate VLSI architectures for arithmetic operations, with respect to the different element representations. The VLSI architectures are mutually compared with respect to area (A) and time (T ) complexity and area-time performance (AT ). The VLSI model chosen is a linear switch-level RC model. In the polar representation, the nonzero elements of a field are represented by the powers of a primitive element of the field. In the thesis we particularly investigate the properties of arithmetic operations and their corresponding VLSI architectures with respect to the polar representation of the elements of Fermat prime fields. Some new results regarding the applicability of the Fermat number transform when using the polar representation are also presented.
17 citations
Cites background or methods from "Computational Aspects of Vlsi"
...For example, in Chapter 2 of [104], Ullman gives an introduction to the area of AT performance....
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...A survey of computational algorithms and their VLSI implementation is given by Ullman [104]....
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...The notations O and are conventionally used in the area of VLSI complexity, see for example Ullman [104]....
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Book•
25 Aug 1989TL;DR: This book provides a superb introduction to and overview of the MIT PI System for custom VLSI placement and routing and provides a balanced and comprehensive presentation of the key ideas and techniques used in PI.
Abstract: This book provides a superb introduction to and overview of the MIT PI System for custom VLSI placement and routing. Alan Sher man has done an excellent job of collecting and clearly presenting material that was previously available only in various theses, confer ence papers, and memoranda. He has provided here a balanced and comprehensive presentation of the key ideas and techniques used in PI, discussing part of his own Ph. D. work (primarily on the place ment problem) in the context of the overall design of PI and the contributions of the many other PI team members. I began the PI Project in 1981 after learning first-hand how dif ficult it is to manually place modules and route interconnections in a custom VLSI chip. In 1980 Adi Shamir, Leonard Adleman, and I designed a custom VLSI chip for performing RSA encryp tion/decryption [226]. I became fascinated with the combinatorial and algorithmic questions arising in placement and routing, and be gan active research in these areas. The PI Project was started in the belief that many of the most interesting research issues would arise during an actual implementation effort, and secondarily in the hope that a practically useful tool might result. The belief was well-founded, but I had underestimated the difficulty of building a large easily-used software tool for a complex domain; the PI soft ware should be considered as a prototype implementation validating the design choices made."
17 citations
01 Apr 1993
TL;DR: A new general optimisation paradigm, called stochastic probe, is proposed to integrate the advantages of the above two approaches and shows that all three new algorithms produce significantly better solutions than the LPK algorithm reported by Lee, Park and Kim.
Abstract: The paper studies the multiway graphpartition problem for VLSI circuit partition. Given a graph representing a VLSI circuit, the graph vertices are partitioned into mutually exclusive subsets to minimise the total weights for edges crossing the subsets under the constraint that the vertex weights are evenly distributed among the subsets. Simulated annealing and tabu search are adapted to solve this problem based on a special neighbourhood design. A new general optimisation paradigm, called stochastic probe, is then proposed to integrate the advantages of the above two approaches. Extensive experimental study shows that all three new algorithms produce significantly better solutions than the LPK algorithm reported by Lee, Park and Kim, and that the stochastic probe algorithm always produces the best solution among all the four algorithms with a running time comparable with that for the LPK algorithm.
17 citations