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Computational Aspects of Vlsi
01 Jan 1984-
About: The article was published on 1984-01-01 and is currently open access. It has received 862 citations till now. The article focuses on the topics: Very-large-scale integration.
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TL;DR: The primal-dual contact representations of planar graphs in 2D using circles and triangles were extended in this paper to 3D polyhedra and L-shaped polyhedras.
Abstract: We study contact representations of graphs in which vertices are represented by axis-aligned polyhedra in 3D and edges are realized by non-zero area common boundaries between corresponding polyhedra. We show that for every 3-connected planar graph, there exists a simultaneous representation of the graph and its dual with 3D boxes. We give a linear-time algorithm for constructing such a representation. This result extends the existing primal-dual contact representations of planar graphs in 2D using circles and triangles. While contact graphs in 2D directly correspond to planar graphs, we next study representations of non-planar graphs in 3D. In particular we consider representations of optimal 1-planar graphs. A graph is 1-planar if there exists a drawing in the plane where each edge is crossed at most once, and an optimal n-vertex 1-planar graph has the maximum (4n - 8) number of edges. We describe a linear-time algorithm for representing optimal 1-planar graphs without separating 4-cycles with 3D boxes. However, not every optimal 1-planar graph admits a representation with boxes. Hence, we consider contact representations with the next simplest axis-aligned 3D object, L-shaped polyhedra. We provide a quadratic-time algorithm for representing optimal 1-planar graph with L-shaped polyhedra.
13 citations
17 Jun 1996
TL;DR: This paper shows that bounded-degree trees in some classes of balanced trees, frequently used as search trees, admit strictly upward straight-line drawings with area O(n loglog n).
Abstract: In this paper, we investigate planar upward straight-line grid drawing problems for bounded-degree rooted trees so that a drawing takes up as little area as possible. A planar upward straight-line grid tree drawing satisfies the following four constraints: (1) all vertices are placed at distinct grid points (grid), (2) all edges are drawn as straight lines (straight-line), (3) no two edges in the drawing intersect (planar), and (4) no parents are placed below their children (upward). Our results are summarized as follows. First, we show that a bounded-degree tree T with n vertices admits an upward straight-line drawing with area O(n log log n). If T is binary, we can obtain an O(n log log n)-area upward orthogonal drawing in which each edge is drawn as a chain of at most two orthogonal segments and which has O(n/log n) bends in total. Second, we show that bounded-degree trees in some classes of balanced trees, frequently used as search trees, admit strictly upward straight-line drawings with area O(n loglog n). They include k-balanced trees, red-black trees, BB [α]-trees, and (a, b)-trees. In addition, trees in the same classes admit O(n(loglog n)2)-area strictly upward straight-line drawings that preserve the left-to-right ordering of the children of each vertex. Finally, we discuss an extension of our drawing algorithms to non-upward straight-line drawing algorithms in 2- and 3-dimensions.
13 citations
Cites methods from "Computational Aspects of Vlsi"
...Several tree drawing algorithms [14, 8, 13, 4, 7] adopt this strategy....
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TL;DR: The problem of recovering multipipelines in the presence of faulty stages is addressed and it is shown that the maximum signal delay in any of the pipelines is O(log m), where m is the initial number of pipelines.
Abstract: The problem of recovering multipipelines in the presence of faulty stages is addressed. The stages are assumed to be organized in rows and columns. The pipeline stages are alternated with reconfiguring circuitry which is used for bypassing the faulty stages. The pipelines are configured by programming the switches in a distributed manner using fault information available locally. The configuration algorithm is optimal in the sense that it recovers the maximum number of pipelines under any fault pattern. Probabilistic bounds on the delay (the number of bypassed faulty stages) and yield (the number of nonfaulty pipelines recovered) are derived. It is shown that the maximum signal delay in any of the pipelines is O(log m), where m is the initial number of pipelines. A constant fraction of these pipelines can be recovered with the scheme, as opposed to an exponentially decreasing number when no reconfiguration is used. The reconfiguration scheme can also be used to provide fault-tolerant buses on a wafer. >
13 citations
TL;DR: The DyKOr (Dynamic Knowledge Organization) method combines information that is usually available through execution traces with existing domain knowledge using techniques from machine learning including knowledge compilation, explanation-based learning, and conceptual clustering to improve the quality and content of explanations.
Abstract: The paper presents a methodology for improving the organization of knowledge bases and demonstrates its application for generating the content of explanations. The DyKOr (Dynamic Knowledge Organization) method combines information that is usually available through execution traces with existing domain knowledge using techniques from machine learning including knowledge compilation, explanation-based learning, and conceptual clustering. These techniques allow the separation of the knowledge needed to solve a problem from that which is not required, and the identification of information that is related to the problem but is not explicitly stated. Thus, the analysis performed through the methodology can considerably improve the quality and content of explanations.
The paper describes the implementation of the methodology and how it can be integrated into typical rule-based expert systems. Illustrations of how the method can be used to produce the content for explanations are presented in the context of typical consultation and problem solving expert systems. A discussion of how the information produced by the method can be used to prepare explanations for users with different levels of expertise is also presented.
13 citations
01 May 1993
TL;DR: In this article, the nonzero entries of the coefficient matrix are mapped onto a processor array of size √e × √ e, where e is the number of nonzero elements, n is the total number of equations and e ⩾ n. This results in O(√e) time for each iteration of the method, with a small constant factor.
Abstract: We propose a novel way of solving systems of linear equations with sparse coefficient matrices using iterative methods on a VLSI array. The nonzero entries of the coefficient matrix are mapped onto a processor array of size √e × √e, where e is the number of nonzero elements, n is the number of equations and e ⩾ n. The data transport problem that arises because of this mapping is solved using an efficient routing technique. Preprocessing is carried out on the iteration matrix of the system to compute the routing control-words that are used in the data transfer. This results in O(√e) time for each iteration of the method, with a small constant factor. As compared to existing VLSI methods for solving the problem, the proposed method yields a superior time performance, greater ease of programmability and an area efficient design. We also develop a second implementation of our algorithm that uses a slightly higher number of communication steps, but reduces the number of arithmetic operations to O(log e). The latter algorithm is suitable for many other architectures as well. The algorithm can be implemented in O(log e) time using e processors on a hypercube, shuffle-exchange, and cube-connected-cycles.
13 citations