Book•
Computational Aspects of Vlsi
01 Jan 1984-
About: The article was published on 1984-01-01 and is currently open access. It has received 862 citations till now. The article focuses on the topics: Very-large-scale integration.
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Journal Article•
TL;DR: A new methodology for computing orientation of a gray-tone image by the method of moments is described, accomplished by a new projection method that leads to a fast algorithm of determining orientation.
Abstract: In this paper, a new methodology for computing orientation of a gray-tone image by the method of moments is described. Orientation is an essential feature needed in many image processing and pattern recognition tasks. Computation of moments is accomplished by a new projection method that leads to a fast algorithm of determining orientation. Using a simple architecture, the proposed algorithm can be implemented as a special purpose VLSI chip. The hardware cost of the proposed design is significantly lower compared to that of the existing architecture.
13Â citations
13 Sep 1998
TL;DR: An extraction module is developed which reads in the geometric description of the layout structure and reconstructs the corresponding schematic, which can be fed to an ordinary differential equation solver or compared with the design schematic to validate the correctness of the designed layout.
Abstract: Microelectromechanical systems (MEMS) integrating multidomain sensors and actuators with conventional microelectronic batch fabrication processes are becoming increasingly complex. In order to design systems with large numbers of multi-domain components, we need to use a hierarchical structured design approach, with design at the schematic level instead of the traditional layout representation used in MEMS design. However, since fabrication can only be done from a layout representation, an automatic or manual layout generation from schematic is necessary. It is essential to be able to translate from the layout representation back to the schematic to reason about layout correctness in meeting the schematic’s function as well as to extract geometric parameters for functional simulation. An extraction module is developed which reads in the geometric description of the layout structure and reconstructs the corresponding schematic. This schematic can then be fed to an ordinary differential equation solver or can be compared with the design schematic to validate the correctness of the designed layout. The extraction module also minimizes the number of nodes required to represent the schematic as a netlist. The results presented show the success of the module for some example MEMS designs.
13Â citations
21 Sep 2003
TL;DR: Radial planarity as mentioned in this paper is a generalisation of level planarity, where the vertices are placed on k horizontal lines and the edges are routed as curves without crossings, and it is decidable in linear time.
Abstract: Every planar graph has a concentric representation based on a breadth first search, see [21]. The vertices are placed on concentric circles and the edges are routed as curves without crossings. Here we take the opposite view. A graph with a given partitioning of its vertices onto k concentric circles is k-radial planar, if the edges can be routed monotonic between the circles without crossings. Radial planarity is a generalisation of level planarity, where the vertices are placed on k horizontal lines. We extend the technique for level planarity testing of [18,17,15,16,12,13] and show that radial planarity is decidable in linear time, and that a radial planar embedding can be computed in linear time.
12Â citations
28 Aug 1989
TL;DR: The Nested Interactive Array Language, Nial has several constructs and primitives which express independent computations that can be executed in parallel and how they might be implemented on a variety of architectures are described.
Abstract: The Nested Interactive Array Language, Nial has several constructs and primitives which express independent computations that can be executed in parallel. This paper describes these constructs and indicates how they might be implemented on a variety of architectures. A number of well-known parallel algorithms are presented in Nial and their effectiveness discussed.
12Â citations
TL;DR: An efficient geometrical design rule checker is proposed, based on operations on quadtrees, which represent VLSI mask layouts, with time complexity O(N), where N is the number of polygons in the mask.
Abstract: An efficient geometrical design rule checker is proposed, based on operations on quadtrees, which represent VLSI mask layouts. The time complexity of the design rule checker is O(N), where N is the number of polygons in the mask. A pseudoPascal description is provided of all the important algorithms for geometrical design rule verification.
12Â citations