Book•
Computational Aspects of Vlsi
01 Jan 1984-
About: The article was published on 1984-01-01 and is currently open access. It has received 862 citations till now. The article focuses on the topics: Very-large-scale integration.
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12 Mar 1990
TL;DR: The author describes an algebraic model of design space that helps incorporate this flexibility into module generators in function module generators.
Abstract: The design space exploration has been a goal of silicon-compilation for quite a while. But the function module generators (for functions such as adder, shifter and multiplier) do not have a concise model for their design space. This limits their ability to explore the design space. Hence they produce a fixed design which in turn hampers the design space exploration ability of the design synthesis environment. The author describes an algebraic model of design space that helps incorporate this flexibility into module generators. >
8 citations
11 Feb 2013
TL;DR: This work introduces an approach for implementing physical models on FPGAs that applies graph theoretic techniques to make use of a physical model's natural structure--tree, ring, chain, etc.--resulting in model execution speedups, and presents a simulated annealing approach with custom cost and neighbor functions that can map any physical model onto an FPGA with low wire costs.
Abstract: Physical models utilize mathematical equations to model physical systems like airway mechanics, neuron networks, or chemical reactions. Previous work has shown that physical models can execute fast on FPGAs (field-programmable gate arrays). We introduce an approach for implementing physical models on FPGAs that applies graph theoretic techniques to make use of a physical model's natural structure--tree, ring, chain, etc.--resulting in model execution speedups. A first phase of the approach maps physical model equations to a structured virtual PE (processing element) graph using graph theoretic folding techniques. A second phase maps the structured virtual PE graph to physical PE regions on an FPGA using graph embedding theory. We also present a simulated annealing approach with custom cost and neighbor functions that can map any physical model onto an FPGA with low wire costs. Average circuit speedup improvements over previous works for various physical models are 65% using the graph embedding and 35% using the simulated annealing approach. Each approach's more efficient use of FPGA resources also enables larger models to be implemented on an FPGA device.
8 citations
Cites methods from "Computational Aspects of Vlsi"
...We utilize the H-tree construction technique that is used in VLSI for the layout of tree architectures onto optimally sized square hosts [23][30]....
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...VLSI design has also utilized graph embedding techniques, including minimizing communication between a binary-tree structured processor network implemented on an optimally sized square [23]....
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Dissertation•
01 Jan 1999
TL;DR: This dissertation presents a system-level approach to localize computation and communication in an efficient computing platform and presents a new area I/O systolic architecture to exploit the physical locality of planar data streams by processing the data where it falls.
Abstract: Portable multimedia systems require high performance, high efficiency, and the ability to exploit future gigascale VLSI technology. Limits of fixture on-chip interconnect, as projected in the National Technology Roadmap for Semiconductors (NTRS), increase communication costs and prevent the scaling of existing architectural approaches. New architectures must better exploit physical data locality to reduce the demand on global interconnects. This dissertation presents a system-level approach to localize computation and communication in an efficient computing platform. Research contributions include system models that capture interconnect-demand and describe architectures in gigascale technologies, and systolic synthesis procedures to map algorithms for area I/O arrays using planar streams. The system models average 60% more accurate in predictions of wire demand than existing stochastic models. A new area I/O systolic architecture is presented to exploit the physical locality of planar data streams by processing the data where it falls. New synthesis procedures for planar data streams presented in this thesis provide a three times increase in performance over previous techniques. Simulation results show that area I/O can provide additional average speedups of 16 times by exploiting additional data parallelism. This systolic array is approximately two orders of magnitude more area and power efficient than DSP and general-purpose microprocessors.
8 citations
Cites methods from "Computational Aspects of Vlsi"
...A processor with two units is optimal under the AT(2) rating (area·time(2)) [86] because this processor grain-size provides the best computation latency in the minimum chip area....
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01 Dec 1986
TL;DR: A situation where each one of two processors has access to a different convex function fi, i = 1, 2, defined on a common bounded domain is considered, to determine protocols under which the number of exchanged messages is minimized.
Abstract: We consider a situation where each one of two processors has access to a different convex function fi, i = 1, 2, defined on a common bounded domain. The processors are to exchange a number of binary messages, according to some protocol, until they find a point in the domain at which f1+f2 is minimized, within some prespecified accuracy ?. Our objective is to determine protocols under which the number of exchanged messages is minimized.
8 citations
01 Mar 1992
TL;DR: Two distributed schemes are provided for embedding and reconfiguration of binary trees in faulty hypercubes based on a key concept called free dimension, which can be used to partition a cube into subcubes such that each subcube contains at most one faulty node.
Abstract: Considers the problem of embedding and reconfiguring binary tree structures in faulty hypercubes The authors assume that the number of faulty nodes is about n, where n is the number of dimensions of the hypercube; they further assume that the location of faulty nodes are known The embedding techniques are based on a key concept called free dimension, which can be used to partition a cube into subcubes such that each subcube contains at most one faulty node Using this approach, two distributed schemes are provided for embedding and reconfiguration of binary trees in faulty hypercubes >
8 citations