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Computational Aspects of Vlsi
01 Jan 1984-
About: The article was published on 1984-01-01 and is currently open access. It has received 862 citations till now. The article focuses on the topics: Very-large-scale integration.
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05 Jun 1988
TL;DR: The authors present O(n/sup 2//p) time solutions to several geometric problems which require global transfer of information such as labeling connected regions, computing the convexity and intersections of multiple regions, and computing several distance functions.
Abstract: Optimal parallel solutions are presented to several geometric problems on an n*n image on a fixed-size linear array with p processors, where 1 >
8 citations
Cites methods from "Computational Aspects of Vlsi"
...Several definitions of connectivity can be used [ 25 ]....
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01 Jan 1988
TL;DR: A new lower bound on the average interconnect (edge) length in terms of diameter and symmetry of the topology is used, and shows that many interconnection topologies of today’s multicomputers do not scale well in the physical world with 3 dimensions.
Abstract: Getting rid of the ‘von Neumann’ bottleneck in the shift from sequential to non-sequential computation, a new communication bottleneck arises because of the interplay between locality of computation, communication, and the number of dimensions of physical space. As a consequence, realistic models for non-sequential computation should charge extra for communication, in terms of time and space. We give a proposal for this that is more subtle, but mutatis mutandis similar to the transition from unit cost to logarithmic cost in the sequential Random Access Machine model. The space cost of communication is related with the topology of the communication graph. We use a new lower bound on the average interconnect (edge) length in terms of diameter and symmetry of the topology. This lower bound is technology independent, and shows that many interconnection topologies of today’s multicomputers do not scale well in the physical world with 3 dimensions.
7 citations
01 Jan 2005
TL;DR: The main results are linear time algorithms both for the planarity test and for the computation of an embedding, and thus a drawing, which use and generalise PQ-trees, which are a data structure for efficient planarity tests.
Abstract: In this thesis we generalise the notion of level planar graphs in two directions: track planarity and radial planarity. Our main results are linear time algorithms both for the planarity test and for the computation of an embedding, and thus a drawing. Our algorithms use and generalise PQ-trees, which are a data structure for efficient planarity tests. A graph is a level graph, if it has a partition of the vertices in levels such that the vertices of each level can be placed on a horizontal line and the edges are strictly downwards. It is level planar if there are no edge crossings. Level planarity can be tested efficiently in linear time by sophisticated and complex algorithms. Level graphs exclude horizontal edges between vertices on the same level. Such edges are allowed by our track graphs. In radial level graphs the vertices of each level are placed on concentric circles and the edges are outwards. We characterise essential differences between level and radial level planar graphs, which are expressed by level non-planar biconnected components called rings. The presence of rings introduces the particular problem of the nesting of non-connected components. Further, we study forbidden subgraphs which destroy radial level planarity. The track and circle extensions are combined to form circle graphs, which allow edges along the concentric circles. Level planar graphs arise as a specialisation of directed acyclic graphs that are usually drawn by the Sugiyama algorithm, which avoids edge crossings. Applications of level or track planar drawings include for example biochemical pathways, entity relationship and UML class diagrams, or flow charts which occur for example in project management. Typical applications of radial drawings are social networks.
7 citations
Cites background from "Computational Aspects of Vlsi"
...It is well known that every planar graph has a concentric representation based on a BFS traversal [155]....
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13 Nov 1994
TL;DR: This work addresses the problem of automatically generating layouts for graphs using graph grammars by identifying the most efficient and scalable approaches to graph generation.
Abstract: We address the problem of automatically generating layouts for graphs using graph grammars.
7 citations
Cites methods from "Computational Aspects of Vlsi"
...Carpano [4] and the H-tree algorithm of Ullman [ 18 ] for VLSI-Design implemented as attribute graph grammar are shown in Fig. 3....
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TL;DR: Although the PFN is a dynamic connection network, it shows low delay and high throughput for the applications that have locality, and the proposed performance model effectively highlights this locality factor.
7 citations