Book•
Computational Aspects of Vlsi
01 Jan 1984-
About: The article was published on 1984-01-01 and is currently open access. It has received 862 citations till now. The article focuses on the topics: Very-large-scale integration.
Citations
More filters
TL;DR: An optimal algorithm for layout of CMOS functional cells, in the gate-matrix style, is proposed and optimality of this bound is established by proving that there are instances of the problem that require ω(log n) rows.
7 citations
01 Jan 1988
TL;DR: It is shown that the proposed systolic algorithm for finding bridges in an n-node connected graph is an improvement over the previously known algorithm on a n × n array of processing elements, as proposed by Attalah and Kosaraju.
Abstract: A new systolic algorithm for finding bridges in an n-node connected graph is proposed in this paper. The algorithm is executable on a n × n array of processing elements. It is shown that our algorithm is an improvement over the previously known algorithm for an n-node connected graph on a n × n array of processing elements, as proposed by Attalah and Kosaraju. The improvement both in area and time complexity is significant. Moreover, the control structure required for implementing the proposed algorithm on a systolic array is simpler.
7 citations
TL;DR: This paper presents the first polynomial algorithm which runs in O(n^2log@D) time for finding an optimal vertex ranking of a block graph G, where n and @D denote the number of vertices and the maximum degree of G, respectively.
Abstract: A vertex ranking of an undirected graph G is a labeling of the vertices of G with integers such that every path connecting two vertices with the same label i contains an intermediate vertex with label j>i. A vertex ranking of G is called optimal if it uses the minimum number of distinct labels among all possible vertex rankings. The problem of finding an optimal vertex ranking for general graphs is NP-hard, and NP-hard even for chordal graphs which form a superclass of block graphs. In this paper, we present the first polynomial algorithm which runs in O(n^2log@D) time for finding an optimal vertex ranking of a block graph G, where n and @D denote the number of vertices and the maximum degree of G, respectively.
7 citations
Dissertation•
01 Jan 1999
TL;DR: The result of the global optimization of the new convex models is a global placement which is further improved using a Tabu search based iterative technique and a new scheme based on Utility Theory for selecting and assigning nets to tracks in the channel.
Abstract: The design of modern integrated circuits is overwhelmingly complicated due to the enormous number of cells in a typical modern circuit. To deal with this di culty, the design procedure is broken down into a set of disjoint tasks. Circuit layout is the task that refers to the physical realization of a circuit from its functional description. In circuit layout, a connection-list called netlist of cells and nets is given. Placement and routing are subtasks associated with circuit layout and involve determining the geometric locations of the cells within the placement area and connecting cells sharing common nets. In performing the placement and the routing of the cells, minimum placement area, minimum delay and other performance constraints need to be observed. In this work, we propose and investigate new approaches to placement and routing problems. Speci cally, for the placement subtask, we propose new convex programming formulations to estimate wirelength and force cells to spread within the placement area. As opposed to previous approaches, our approach is partitioning free and requires no hard constraints to achieve cell spreading within the placement area. The result of the global optimization of the new convex models is a global placement which is further improved using a Tabu search based iterative technique. The e ectiveness, robustness and superiority of the approach are demonstrated on a set of nine benchmark industrial circuits. With regard to the routing subtask, we propose a hybrid methodology that combines Tabu search and Stochastic Evolution as a search engine in a new channel router. We also propose a new scheme based on Utility Theory for selecting and assigning nets to tracks in the channel. In this scheme, problem-domain information expressed in the form of utility functions is used to guide the search engine to explore the search space e ectively. The e ectiveness and robustness of the approach is demonstrated on ve industrial benchmarks.
7 citations
Cites background from "Computational Aspects of Vlsi"
...The steps of the VLSI design cycle can be brie y outlined as follows [56, 62]:...
[...]
...The optimization problems that have to be solved during the circuit layout are intractable [39, 62]....
[...]
TL;DR: In this paper, hexagonal mesh is selected as the host topology in which two different networks for update and query operation are embedded and the proposed design is simple to implement as well as allows high throughput.
Abstract: Dictionary machine is an important VLSI system performing high speed data archival operations. In this paper, we present a design which can efficiently implement dictionary machines in VLSI processor arrays. In order to effectively process the operations of dictionary machine, hexagonal mesh is selected as the host topology in which two different networks for update and query operation are embedded. The proposed design is simple to implement as well as allows high throughput.
7 citations