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Computational Aspects of Vlsi
01 Jan 1984-
About: The article was published on 1984-01-01 and is currently open access. It has received 862 citations till now. The article focuses on the topics: Very-large-scale integration.
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Dissertation•
01 Jan 1992
TL;DR: This thesis describes a systematic method for the synthesis of control signals for systolic arrays that are realised in hardware by replacing the domain predicates in the initial program specification by a system of uniform recurrence equations by means of data pipelining.
Abstract: The distinguishing features characteristic of systolic arrays are synchrony of computations, local and regular connections between processors and massive decentralised parallelism. The potential of the systolic array lies in its suitability for VLSI fabrication and its practicality for a variety of application areas such as signal or image processing and numeric analysis. With the increasing possibilities promised by advances in VLSI technology and computer architecture, more and more complex problems are now solvable by systolic arrays. This thesis describes a systematic method for the synthesis of control signals for systolic arrays that are realised in hardware. Control signals ensure that the right computations are executed at the right processors at the right time. The proposed method applies for iterative algorithms defined over a domain that can be expressed by a convex set of integer coordinates. Algorithms that can be implemented as systolic arrays can be expressed this way; a large subclass can be phrased as affine (or uniform) recurrence equations in the functional style and as nested loops in the imperative style. The synthesis of control signals from a program specification is a process of program transformation and construction. The basic idea is to replace the domain predicates in the initial program specification which constitute the abstract specification of control signals by a system of uniform recurrence equations by means of data pipelining. Then, systolic arrays with a description of both data and control signals can be obtained by a direct application of the standard space-time mapping technique.
7Â citations
Dissertation•
20 May 1991
TL;DR: This thesis presents some of the issues involved in the design of an array of special-purpose processors connected in a mesh, for fast real time computation of the Singular Value Decomposition.
Abstract: The Singular Value Decomposition (SVD) is an important matrix factorization with applications in signal processing, image processing and robotics. This thesis presents some of the issues involved in the design of an array of special-purpose processors connected in a mesh, for fast real time computation of the SVD. The systolic array implements the Jacobi method for the SVD. This involves plane rotations and inverse tangent calculations and is implemented e ciently in hardware using the COordinate Rotation DIgital Computer (CORDIC) technique. A six chip custom VLSI chip set for the processor was initially developed and tested. This helped identify several bottlenecks and led to an improved design of the single chip version. The single chip implementation incorporates several enhancements that provide greater numerical accuracy. An enhanced architecture which reduces communication was developed within the constraints imposed by VLSI. The chips were fabricated in a 2:0 CMOS n-well process using a semicustom design style. The design cycle for future chips can be considerably reduced by adopting a symbolic layout style using high-level VLSI tools such as Octtools from the University of California, Berkeley.
7Â citations
Cites background from "Computational Aspects of Vlsi"
...The hardware costs involved in these operations are: Shifter: The area complexity [34] of the shifter grows as O(t1 Maximum Shift required) = O(t1 p t1) = O(t1 )....
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01 Jan 2000
TL;DR: This chapter serves as an introduction to the study of parallel algorithms, in particular how they differ from conventional algorithms, how they were designed, and how they are analyzed to evaluate their speed and cost.
Abstract: This chapter serves as an introduction to the study of parallel algorithms, in particular how they differ from conventional algorithms, how they are designed, and how they are analyzed to evaluate their speed and cost.
7Â citations
TL;DR: It is shown how the balnced binary tree technique can be effectively utilised (to solve problems of size n and implying a balanced binary tree xith n leaves) on a square mesh of n processing elements.
7Â citations
TL;DR: The main result is that every uniform regular network can be simulated by a totalistic systolic network.
7Â citations