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Computational Aspects of Vlsi
01 Jan 1984-
About: The article was published on 1984-01-01 and is currently open access. It has received 862 citations till now. The article focuses on the topics: Very-large-scale integration.
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TL;DR: This tutorial provides the reader with a broad perspective of this important field and the pedagogy needed to understand the basic principles of digital multiplication, representing a mix of speed/complexity tradeoffs.
Abstract: The successful design of digital signal processing (DSP) systems and subsystems is often predicated on realizing fast multiplication in digital hardware. This tutorial provides the reader with a broad perspective of this important field and the pedagogy needed to understand the basic principles of digital multiplication. Both conventional and nonconventional methods of implementing multiplication, representing a mix of speed/complexity tradeoffs, are presented. Some are based on traditional shift-add structures, whereas others strive for greater mathematical sophistication. Topics include stand-alone fixed-point multipliers, cellular arrays, memory intensive policies, homomorphic systems, and modular arithmetic. >
110 citations
TL;DR: A look at the technology roadmap and what it means to computer architects, updating the authors' views of six years ago.
Abstract: With the scaling of technology promising increases in chip frequency and especially transistor density, system designers must make trade-offs for a rapidly moving target. They must constantly deal with area, time, power, reliability, and technology design trade-offs as well as enormous design complexity at the same time. The driving force in design innovation is the rapid advance in technology. As technology advances and feature size shrinks, the three other design considerations benefit from one process generation to another, resulting in higher speed, smaller area, and reduced power consumption. Here, we look at the technology roadmap and what it means to computer architects, updating our views of six years ago.
110 citations
TL;DR: It is shown how to extend the solution for the approximate distribution problem to an optimal probabilistic algorithm for the exact distribution problem on a similar class of expander graphs.
Abstract: A solution to the following fundamental communication problem is presented. Suppose that n tokens are arbitrarily distributed among n processors with no processor having more than K tokens. The problem is to specify a bounded-degree network topology and an algorithm that can distribute the tokens uniformly among the processors.The first result is a tight $\Theta (K + \log n)$ bound on the complexity of this problem. It is also shown that an approximate version of this problem can be solved deterministically in $O(K + \log n)$ on any expander graph with sufficiently large expansion factor.In the second part of this work, it is shown how to extend the solution for the approximate distribution problem to an optimal probabilistic algorithm for the exact distribution problem on a similar class of expander graphs. Note that communication through an expander graph is a necessary condition for an $O(K + \log n)$ solution of the problem.These results have direct applications to the efficient implementation of many...
110 citations
TL;DR: A survey of results on the exact bandwidth, edgesum, and profile of graphs is provided in this paper, with a bibliography of work in these areas provided by Chinn, Chvatalova, Dewdney, and Gibbs.
Abstract: This article provides a survey of results on the exact bandwidth, edgesum, and profile of graphs. A bibliography of work in these areas is provided. The emphasis is on composite graphs. This may be regarded as an update of the original survey of solved bandwidth problems by Chinn, Chvatalova, Dewdney, and Gibbs [10] in 1982. Also several of the application areas involving these graph parameters are described. © John & Sons, Inc. Graph Theory 31: 75–94, 1999
105 citations
Cites background from "Computational Aspects of Vlsi"
...Several papers discuss this application areas including Adolphson and Hu[1], Bhatt and Leighton[4], Diaz[21], Miller[75], Shing and Hu[85] and Ullman[92]....
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TL;DR: It is shown that carry-save arithmetic can be used for the operations of ACS recursion, allowing each word-level operation to be pipelined and carried out by an efficient bit-level systolic array.
Abstract: The main part of the Viterbi algorithm (VA) is a nonlinear feedback loop, the ACS recursion (add-compare-select recursion), which presents a bottleneck for high-speed implementations and cannot be circumvented by standard means. Because the two operations of the loop form an algebraic structure called semiring, it is shown that the ACS recursion of the Viterbi algorithm can therefore be written as a linear vector recursion. This allows the authors to employ the powerful techniques of parallel processing and pipelining, known for conventional linear systems, to achieve high throughput rates. Since the VA can be written as a linear vector recursion, it can be implemented by systolic arrays. For the class of shuffle exchange codes to be decoded by the Viterbi algorithm hardware-efficient code-optimized arrays are presented. It is shown that carry-save arithmetic can be used for the operations of ACS recursion, allowing each word-level operation to be pipelined and carried out by an efficient bit-level systolic array. >
104 citations