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Computational Aspects of Vlsi
01 Jan 1984-
About: The article was published on 1984-01-01 and is currently open access. It has received 862 citations till now. The article focuses on the topics: Very-large-scale integration.
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TL;DR: Parallel algorithms for several important combinatorial problems such as the all nearest smaller values problem, triangulating a monotone polygon, and line packing are presented.
Abstract: Parallel algorithms for several important combinatorial problems such as the all nearest smaller values problem, triangulating a monotone polygon, and line packing are presented. These algorithms achieve linear speedups on the pipelined hypercube, and provably optimal speedups on the shuffle-exchange and the cube-connected-cycles for any number p of processors satisfying 1 >
5 citations
TL;DR: A statistical zero-knowledge authentication scheme is described for security control in on-line database transaction processing systems (OLTP) that uses probabilistic quorum protocols to validate users using their biometrical characteristics.
Abstract: A statistical zero-knowledge authentication scheme is described for security control in on-line database transaction processing systems (OLTP). This scheme uses probabilistic quorum protocols to validate users using their biometrical characteristics (such as speech, handwriting and keyboard characteristics). This authentication scheme can be implemented using the present-day smart card technology.
5 citations
04 Mar 1994
TL;DR: The main goal is to parametrize the VLSI architecture so that it can be implemented under various packaging constraints including the available number of I/O pins, available chip-area, and certain restrictions on maximum wire length.
Abstract: This paper presents a methodology for designing folded VLSI networks for implementing tensor-product forms. Using tensor-products leads to very efficient expressions for a large number of computations in digital signal processing and matrix arithmetic. The resulting networks can trade-off total time delay with I/O bandwidth and chip area. The main goal is to parametrize the VLSI architecture so that it can be implemented under various packaging constraints including the available number of I/O pins, available chip-area, and certain restrictions on maximum wire length. Our methods result in folded VLSI networks with optimal AT/sup 2/ trade-off for digital filtering and multidimensional transforms, where A is the total area of the VLSI circuit (or chip) and T is its total time delay. >
5 citations
02 Jan 1987
TL;DR: In this paper, the authors considered the problem of information sharing in a synchronous broadcasting network and gave an O(n log 2 p + p )-time algorithm, where p is the number of nodes in the broadcasting network.
Abstract: In this paper we consider a synchronous broadcasting network, a distributed computation model which represents communication networks that are used extensively in practice. We consider a basic problem of information sharing: the computation of the multiple identification function. That is, given a network of p processors, each of which contains an n -bit string of information, how can every processor compute efficiently the subset of processors which have the same information as itself? The problem was suggested by Yao as a generalization of the two-processor case studied in his classic paper on distributed computing (Yao, 1979). The naive way to solve this problem takes O( np ) communication time, where a time unit is the time to transfer one bit. We present an algorithm which takes advantage of properties of strings and is O ( n log 2 p + p ) time. A simulation of sorting networks by the distributed model yields an O ( n log p + p ) (impractical) algorithm. By applying Yao's probabilistic implementation of the two-processor case to both algorithm we get probabilistic versions (with small error) where n is replaced by log n in the complexity expressions. We also present lower bounds for the problem: an Ω( n ) and an Ω( p ) bound are shown.
5 citations
01 Nov 1986
TL;DR: It is shown that essentially the same hounds apply to sorting-like problems which produce far fewer output bits, and one of the first methods to account fully for families of networks where the limitations to information flow cannot be analyzed by separator theory is given.
Abstract: We investigate information flow for three distinct kinds of VLSI problems. Included among our results are the following. • The VLSI complexity of sorting-related problems, such as element uniqueness, is analyzed. The chief issue is what proof methodologies can substitute for the literal transport of output data that has been traditionally used to certify information flow for these kinds of problems. • An infinite hierarchy of generalized fooling set information measures is established, and an exponential gap is shown to exist between adjacent levels in the hierarchy. Although this hierarchy provides new proof strategies which can simplify alternative arguments , its basic contribution is to expose hidden weaknesses intrinsic to fooling set formalizations. • The area-time tradeoff is analyzed for a VLSI problem with fewer input bits than data flow. The chief issue turns out to be a nonuniformity in the circuit specification, which impedes the use of Kolmogorov complexity. Transitivity and approximate correct-ness are used to eliminate these irregularities. • We give one of the first methods to account fully for families of networks where the limitations to information flow cannot be analyzed by separator theory. In the process of analyzing these problems, we develop a better understanding of the issues underlying information transfer in VLSI circuits, and develop new ways to account for the intrinsic complexity of VLSI problems and the inherent bottlenecks in some communication networks. Permission to copy without fee all or part of this material is granted provided that the copies are not made or distributed for direct commercial advantage, the ACM copyright notice and the title of the publication and its date appear, and notice is given that copying is by permission of the Association for Computing Machinery. To copy otherwise, or to republish, requires a fee and/or specific permission. The question of lower bounds for VLSI sorters is essentially completely solved in the collections of results by [Bilardi andingly, all of the lower bounds proofs need a massive number of output bits (at least an amount proportional to the internal information flow.) Are so many output bits really necessary? We show that essentially the same hounds apply to sorting-like problems which produce far fewer output bits. (The only exception is an AT/IogA tradeoff, due to Bilardi and Preparata, which results, in part, from a flow of output bits that necessarily exceeds the size of the circuit, and which must therefore be pipelined.) We …
5 citations
Cites methods from "Computational Aspects of Vlsi"
...Generalizing from [Ullman, 1984], let an r-fold fooling set for a function f:X-Y, with size N input, X~{0,1} -v, output Y E{0,1} s, and for a partition ~ = (XL,X~,yL,YR) , be a set F of r-tuples, each of which, comprises r input assignments with the property that for any pair of distinct tuples…...
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...The PS definition might be strengthened as in [Ullman 1984], by maximizing, over all subsets of the input, the minimization, over all partitions that bisect the subset into two (approximately) equally sized subsets, the information that must be exchanged, in the sense of PS....
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...(See PS [Papadimitriou and Sipser, 1982], AUY [Aho, Ullman and Yannakakis, 1983], and [Ullman, 1984].)...
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