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Computational Aspects of Vlsi
01 Jan 1984-
About: The article was published on 1984-01-01 and is currently open access. It has received 862 citations till now. The article focuses on the topics: Very-large-scale integration.
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01 Jan 1987
TL;DR: The Integrated Design Aides toolset is a set of VLSI CAD software programs that have been developed to make the most effective use possible of a designer’s time and centers around a constraint-based, symbolic language called IMAGES and a compacter methodology.
Abstract: The Integrated Design Aides (IDA) toolset is a set of VLSI CAD software programs that have been developed to make the most effective use possible of a designer’s time. IDA incorporates a number a layout synthesis tools capable of generating both structured circuits, such as ALU’s, and random logic. The system centers around a constraint-based, symbolic language called IMAGES and a compacter methodology. This paper describes IDA, its capabilities, techniques, and status.
5 citations
20 May 2015
TL;DR: This paper proposes two modular multiplication architectures based on modified serial montgomery algorithm for 2048-bit RSA by limiting the integer modulo that has sequence of A094358, a very simple and fast modular multiplication hardware can be developed.
Abstract: RSA (Rivest, Shamir, Adleman) is one of the most widely used cryptographic algorithms worldwide to perform data encryption and decryption. An essential step in RSA computation lies on its modular multiplication which is relatively expensive and time consuming to be implemented in hardware. This paper proposes two modular multiplication architectures based on modified serial montgomery algorithm for 2048-bit RSA. By limiting the integer modulo that has sequence of A094358, a very simple and fast modular multiplication hardware can be developed. The first archictecture which incorporates 2048-bit adders performes better in term of latency (19010 Logic Cells, 2048 clock cycles or 0.0022 s), while the second architecture utilizing multiple smaller 128-bit adders offers less area consumption (8926 Logic Cells, 36864 clock cycles or 0.0031 s). An area multiplied with squared latency (AT2) can be used as trade-off parameter for choosing the most suitable design for certain need. For prototyping purpose, we have successfully synthesized and implemented our proposed designs written in VHDL using Altera Quartus II with Cyclone II EP2C70F896C6 FPGA as a target board.
5 citations
01 Dec 1995
TL;DR: The presented fault model uniquely describes all structural changes in the transistor net list that can be caused by spot defects, including faults that connect more than two nets and faults that break a net into more than three parts.
Abstract: The presented fault model uniquely describes all structural changes in the transistor net list that can be caused by spot defects, including faults that connect more than two nets and faults that break a net into more than two parts. The developed analysis method extracts the complete set of realistic faults from the layout and for each fault computes the probability of occurrence.
5 citations
Cites methods from "Computational Aspects of Vlsi"
...To determine the maximal connectivity faults, McCreigth's algorithm [15] can be applied reporting all pairs of intersecting defect sensitive areas....
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TL;DR: The optical expander described utilizes high-speed and high-space-bandwidth-product connections that are provided by optical beams in three dimensions and uses an optical matrix-vector multiplier and an array of N threshold devices.
Abstract: An optical system called the optical expander is described and investigated. The optical expander electro-optically expands an optical Boolean pattern encoded in d bits into an optical pattern of size N bits. It is assumed that d is equal to c log(2)N for some constant c, and each expanded pattern is orthogonal to the others. Two different architectures to implement the optical expander are described: one uses an optical matrix-vector multiplier and an array of N threshold devices; the other uses log(2)N novel reflection-transmission switching cells. These architectures are analyzed in terms of size, energy requirement, and speed. The optical expander described utilizes high-speed and high-space-bandwidth-product connections that are provided by optical beams in three dimensions. Potential applications, holographic memory, and message routing systems are also discussed.
5 citations
Book•
03 Sep 2011
TL;DR: This work shows how to turn a regular expression into an O(s) space representation of McNaughton and Yamada's NFA, where s is the number of NFA states, and shows that the DFA produced from the NFA is as much as one order of magnitude smaller than DFA's constructed from the two other NFA's.
Abstract: We show how to turn a regular expression into an O(s) space representation of McNaughton and Yamada's NFA, where s is the number of NFA states. The standard adjacency list representation of McNaughton and Yamada's NFA takes up s+s 2 space in the worst case. The adjacency list representation of the NFA produced by Thompson takes up between 2r and 5r space, where r s in general, and can be arbitrarily larger than s. Given any set T of NFA states, our representation can be used to compute the set N of states one transition away from the states in T in optimal time O(jTj + jNj). McNaughton and Yamada's NFA requires (jTj jNj) in the worst case. Using Thompson's NFA, the equivalent calculation requires (r) time in the worst case. An implementation of our NFA representation connrms that it takes up an order of magnitude less space than McNaughton and Yamada's machine. An implementation to produce a DFA from our NFA representation by subset construction shows linear and quadratic speedups over subset construction starting from both Thompson's and McNaughton and Yamada's NFA's. It also shows that the DFA produced from our NFA is as much as one order of magnitude smaller than DFA's constructed from the two other NFA's.
5 citations