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Journal ArticleDOI

Computer-Aided Design of Integrated Circuits

01 Apr 1986-IEEE Computer (IEEE)-Vol. 19, Iss: 4, pp 19-36
About: This article is published in IEEE Computer.The article was published on 1986-04-01. It has received 26 citations till now. The article focuses on the topics: IC layout editor & Mixed-signal integrated circuit.
Citations
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Proceedings ArticleDOI
07 Apr 2002
TL;DR: A fast but reliable way to detect routing criticalities in VLSI chips by using a congestion estimator for a dynamic avoidance of routability problems in one single run of the placement algorithm.
Abstract: We present a fast but reliable way to detect routing criticalities in VLSI chips. In addition, we show how this congestion estimation can be incorporated into a partitioning based placement algorithm. Different to previous approaches, we do not rerun parts of the placement algorithm or apply a post-placement optimization, but we use our congestion estimator for a dynamic avoidance of routability problems in one single run of the placement algorithm. Computational experiments on chips with up to 1,300,000 cells are presented: The framework reduces the usage of the most critical routing edges by 9.0% on average, the running time increase for the placement is about 8.7%. However, due to the smaller congestion, the running time of routing tools can be decreased drastically, so the total time for placement and (global) routing is decreased by 47% on average.

134 citations

Journal ArticleDOI
Wiederhold1
TL;DR: Views provide a useful abstraction in programming languages; views provide a similar abstraction in databases as discussed by the authors, and since databases provide for persistent and shared data storage, view concepts will avoid problems occurring when persistent objects are to be shared.
Abstract: Objects provide a useful abstraction in programming languages; views provide a similar abstraction in databases. Since databases provide for persistent and shared data storage, view concepts will avoid problems occurring when persistent objects are to be shared. Direct storage of objects disables sharing.

133 citations

Journal ArticleDOI
TL;DR: Motion estimation is cast as a problem in energy minimization by modeling the displacement field as a Markov random field using the Mean Field Annealing algorithm, a technique which finds the global or near global minima in nonconvex optimization problems.

27 citations

Journal ArticleDOI
C.F. Fey1, D.E. Paraskevopoulos
01 Jun 1987
TL;DR: In this paper, the authors compared the entire IC-related product cost, design schedule, functionality, and risks to that of designs containing standard devices, including programmable logic devices, gate arrays, standard cells, and full custom, at production volumes of 1 to 100k units per year and at complexities of 5OO to 20 000 gates per device.
Abstract: ASIC design methodologies are assessed from the system designer's point of view by comparing the entire IC-related product cost, design schedule, functionality, and risks to that of designs containing standard devices. ASIC methodologies include programmable logic devices, gate arrays, standard cells, and full custom, all primarily in 2-µm CMOS, at production volumes of 1 to 100K units per year and at complexities of 5OO to 20 000 gates per device. It is shown that "gates per pin" is the key determinant of total IC-related cost. Products containing ASIC cost less than those containing SSI/MSI, since ASICs raise the number of gates per pin from 2 to a range of 40-200. More surprising, products using ASIC devices cost less than products containing combinations of standard LSI/VLSI and SSI/MSI, if their gates per pin is 2-3 times that of the products containing standard devices. Each design methodology has regions, or market segments, where it is competitive. But there are large regions of small cost differences between two ASIC methodologies. Currently, these regions use primarily the older methodologies, i.e., gate arrays at low production volumes and full custom at high volumes. They also provide future opportunities for standard cells. Currently, IC manufacturing cost accounts for about 15 percent of the logic-related total cost, field maintenance for 17 percent, device and system development for 11 percent, and systems related manufacturing cost for 57 percent. These percentages are expected to migrate to 17, 20, 13, and 50 percent, respectively, by 1990. Our ASIC techno-economic assessment is summarized in 27 nomograms, figures, and charts.

18 citations

Book
25 Aug 1989
TL;DR: This book provides a superb introduction to and overview of the MIT PI System for custom VLSI placement and routing and provides a balanced and comprehensive presentation of the key ideas and techniques used in PI.
Abstract: This book provides a superb introduction to and overview of the MIT PI System for custom VLSI placement and routing. Alan Sher man has done an excellent job of collecting and clearly presenting material that was previously available only in various theses, confer ence papers, and memoranda. He has provided here a balanced and comprehensive presentation of the key ideas and techniques used in PI, discussing part of his own Ph. D. work (primarily on the place ment problem) in the context of the overall design of PI and the contributions of the many other PI team members. I began the PI Project in 1981 after learning first-hand how dif ficult it is to manually place modules and route interconnections in a custom VLSI chip. In 1980 Adi Shamir, Leonard Adleman, and I designed a custom VLSI chip for performing RSA encryp tion/decryption [226]. I became fascinated with the combinatorial and algorithmic questions arising in placement and routing, and be gan active research in these areas. The PI Project was started in the belief that many of the most interesting research issues would arise during an actual implementation effort, and secondarily in the hope that a practically useful tool might result. The belief was well-founded, but I had underestimated the difficulty of building a large easily-used software tool for a complex domain; the PI soft ware should be considered as a prototype implementation validating the design choices made."

17 citations

References
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Proceedings ArticleDOI
25 Jun 1984
TL;DR: The Magic layout system incorporates expertise about design rules and connectivity directly into the layout system in order to implement powerful new operations, including: a continuous design-rule checker that operates in background to maintain an up-to-date picture of violations.
Abstract: Magic is a "smart" layout system for integrated circuits. The user interface is based on a new design style called logs, which combines the efficiency of mask-level design with the flexibility of symbolic design. The system incorporates expertise about design rules and connectivity directly into the layout system in order to implement powerful new operations, including: a continuous design-rule checker that operates in background to maintain an up-to-date picture of violations; an operation called plowing that permits interactive stretching and compaction; and routing tools that can work under and around existing connections in the channels. Magic uses a new data structure called corner stitching to achieve an efficient implementation of these operations.

244 citations

J. Soukup1
01 Oct 1981
TL;DR: A general overview of circuit layout, taking a unified approach to various styles of integrated circuits, printed circuit boards, and hybrid circuits, and problems associated with the implementation of a hierarchical system are discussed.
Abstract: This paper gives a general overview of circuit layout, taking a unified approach to various styles of integrated circuits, printed circuit boards, and hybrid circuits. A lot of attention is given to the layout of large and complicated circuits, in particular, to the layout of very-large-scale-integration (VLSI) chips. Though the paper is an overview, and one could almost say a tutorial, it is intended for readers with some basic knowledge of what a circuit layout is and what some of the basic problems are. The main subjects discussed are: assignment of gates, placement methods, loose routing, final routing, and problems associated with the implementation of a hierarchical system. The emphasis is on new, not widely published methods, and on methods that seem to have potential for solving some of the current problems. Practical examples illustrate this rather personal account of circuit layout and sugsest where we may go from here.

211 citations

Proceedings ArticleDOI
27 Jun 1983
TL;DR: The design, implementation and performance of a flat edge-based circuit extractor for NMOS circuits is described, which is capable of analyzing a circuit with 20,000 transistors in less than 30 minutes of CPU time on a VAX 11/780.
Abstract: This paper describes the design, implementation and performance of a fiat edge-based circuit extractor for NMOS circuits. The extractor is able to work on large and complex designs, it can handle arbitrary geometry, and outputs a comprehensive wirelist. Measurements show that the run time of the edge-based algorithm used is linear in size of the circuit, with low implementation overheads. The extractor is capable of analyzing a circuit with 20,000 transistors in less than 30 minutes of CPU time on a VAX 11/780. The high performance of the extractor has changed the role that a circuit extractor played in the design process, as it is now possible to extract a chip a number of times during the same session.

56 citations

Proceedings ArticleDOI
27 Jun 1983
TL;DR: N.mPc, a mature, UNIX (FOOTNOTE: UNIX is a trademark of Bell Laboratories)-based computer-aided design tool is described and its applications to the design of multiple processor hardware/software systems and VLSI are discussed.
Abstract: N.mPc, a mature, UNIX (FOOTNOTE: UNIX is a trademark of Bell Laboratories)-based computer-aided design tool is described. Its structure, performance, and limitations are discussed together with its applications to the design of multiple processor hardware/software systems and VLSI.

16 citations

Proceedings ArticleDOI
01 Jun 1985
TL;DR: This paper describes the VIVID (Vertically Integrated VLSI Design) System developed at the Microelectronics Center of North Carolina, which is based on a symbolic, virtual-grid design methodology that greatly reduces the design time for custom V LSI circuits.
Abstract: This paper describes the VIVID (Vertically Integrated VLSI Design) System developed at the Microelectronics Center of North Carolina. The system is based on a symbolic, virtual-grid design methodology that greatly reduces the design time for custom VLSI circuits. This methodology has made it possible to provide, in a single integrated system, several unique features: technology independent tools for a wide range of MOS processes (CMOS, nMOS, SOI); scale independent circuit designs; open architecture that simplifies both integration with existing tools and creation of new tools; fast layout debugging using symbolic level circuit simulation; and fully automated mask generation and automated chip assembly.

11 citations