Concurrent checking of clock signal correctness
TL;DR: The authors present a new method and self-checking circuit implementation for concurrently checking the correctness of clock distribution network signals in synchronous systems.
Abstract: Traditional concurrent-checking techniques may not detect the occurrence of the transient faults and resulting errors likely to affect clock signals in VLSI systems. The authors present a new method and self-checking circuit implementation for concurrently checking the correctness of clock distribution network signals in synchronous systems.
Citations
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Proceedings Article•
01 Jan 1988
TL;DR: FXT as mentioned in this paper is a software tool which implements inductive fault analysis for CMOS circuits and extracts a comprehensive list of circuit-level faults for any given CMOS circuit and ranks them according to their relative likelihood of occurrence.
Abstract: FXT is a software tool which implements inductive fault analysis for CMOS circuits. It extracts a comprehensive list of circuit-level faults for any given CMOS circuit and ranks them according to their relative likelihood of occurrence. Five commercial CMOS circuits are analyzed using FXT. Of the extracted faults, approximately 50% can be modeled by single-line stuck-at 0/1 fault model. Faults extracted from two circuits are simulated with the switch-level fault simulator FMOSSIM. The test set provided by the circuits' manufacturer, which detects 100% of the single-line stuck-at 0/1 faults, detected between 73% and 89% of the simulated faults.<>
244 citations
13 Mar 2001
TL;DR: Weight based codes are applied to the detection of crosstalk originated errors and a graph theoretic optimization is used in order to reduce the cost of these codes.
Abstract: This work applies weight based codes to the detection of crosstalk originated errors. This type of fault, whose importance grows with device scaling may originate errors that are undetectable by the commonly used error detecting codes in VLSI ICs. Conversely, such errors can be easily detected by weight based codes that, however, have smaller encoding capabilities. In order to reduce the cost of these codes, a graph theoretic optimization is used. Moreover new applications of these codes are explored regarding the synthesis of self-checking FSMs, and the detection of errors related to the clock distribution network.
33 citations
TL;DR: It is found that the clock faults can be detected during manufacturing testing in only 12 percent of cases, and that, in 10 percent of Cases, the undetected clock faults also invalidate the testing procedure itself.
Abstract: Based on real process data of a reference microprocessor, fault models are derived for the manufacturing defects most likely to affect signals of the clock distribution network. Their probability is estimated with Inductive Fault Analysis performed on the actual layout of the reference microprocessor. The effects of the most likely faults have been evaluated by electrical level simulations. We have found that, contrary to common assumptions, only a small percentage of such faults result in catastrophic failures easily detected during manufacturing testing. On the contrary, the majority of such faults lead to local failures not likely to be detected during manufacturing testing, despite their possibly compromising the microprocessor operation and reliability. In particular, we have found that the clock faults can be detected during manufacturing testing in only 12 percent of cases. Even more surprisingly, we have also found that, in 10 percent of cases, the undetected clock faults also invalidate the testing procedure itself.
33 citations
Cites background from "Concurrent checking of clock signal..."
..., [8], [9], [10], [7]) whose use is mandatory for systems oriented to applications with high reliability requirements (e....
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...Online testing techniques for clock signals of high reliability synchronous systems have been documented before [8], [9], [10], [7] and they might be adopted also for general purpose applications....
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01 May 2005
TL;DR: A novel buffer scheme that is able to compensate undesired skews between clocks of a synchronous system in a negligible time upon skew occurrence, thus being suitable also for on-line clock-skew correction and allowing clock skew and duty-cycle fault tolerance, thus increasing process yield and system's reliability.
Abstract: In this paper we propose a novel buffer scheme that is able to compensate undesired skews between clocks of a synchronous system in a negligible time upon skew occurrence, thus being suitable also for on-line clock-skew correction. Clock signals are aligned one with respect to the other, starting from a reference clock, and moving forward among physically adjacent clock signals, thus creating no problem of reference clock's routing. Our solution is also able to compensate clock duty-cycle variations, which have been shown very likely in case of faults, for instance bridgings, affecting the clock distribution network. Compared to alternate solutions, our proposed scheme enables significant reductions in area overhead and power consumption, and is suitable for on-line compensation. Therefore, it allows clock skew and duty-cycle fault tolerance, thus increasing process yield and system's reliability.
19 citations
Cites methods from "Concurrent checking of clock signal..."
...Several methods to test on-line and/or correct clock signals have been published [8, 7, 9, 6], whose use is mandatory for systems for high reliability applications (e....
[...]
10 Oct 2004
TL;DR: Compared to alternative solutions which can be used to compensate/correct skews between couples of clocks, that presented here is definitely faster, features lower area overhead and power consumption, and does not require any initialization phase at the beginning of system operation.
Abstract: We propose a clock buffer that is able to compensate clock skews possibly due to process variations, and correct even more severe skews, as those possibly due to faults affecting the clock distribution network or those due to power supply noise. Compensation/correction is performed instantaneously, during system run-time, upon skew occurrence. Compared to alternative solutions which can be used to compensate/correct skews between couples of clocks, that presented here is definitely faster, features lower area overhead and power consumption, and does not require any initialization phase at the beginning of system operation. Additionally, our proposed buffer is also able to compensate/correct clock duty cycle variations due to process parameter variations, as well as faults affecting the clock distribution network. Also in this case, compensation/correction is accomplished within the same clock cycle of duty-cycle variation occurrence.
15 citations
References
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TL;DR: The design of totally self-checking check circuits for m-out-of-n codes is described and various gate level implementations for the majority detection circuits are presented, although the self- checking capability of the checker does not depend on their particular implementation since they are exhaustively tested by code inputs.
Abstract: The design of totally self-checking check circuits for m-out-of-n codes is described. Totally self-checking m-out-of-n checkers provide an error indication whenever the input is not an m-out-of-n code or whenever a fault occurs within the checker itself. Since the checker checks itself, there is no need for additional maintenance access or periodic exercise of the checker to verify its ability to detect errors. The basic structure of the checker relies on the use of majority detection circuits. Various gate level implementations for the majority detection circuits are also presented, although the self-checking capability of the checker does not depend on their particular implementation since they are exhaustively tested by code inputs. The self-testing checkers for k-out-of-2k codes are discussed in the most detail since the totally self-checking checkers for 1-out-of-n and arbitrary m-out-of-n codes are constructed by first translating the code to a k-out-of-2k code via a totally self-checking translator.
382 citations
12 Sep 1988
TL;DR: FXT is a software tool which implements inductive fault analysis for CMOS circuits and extracts a comprehensive list of circuit-level faults for any given CMOS circuit and ranks them according to their relative likelihood of occurrence.
Abstract: FXT is a software tool which implements inductive fault analysis for CMOS circuits. It extracts a comprehensive list of circuit-level faults for any given CMOS circuit and ranks them according to their relative likelihood of occurrence. Five commercial CMOS circuits are analyzed using FXT. Of the extracted faults, approximately 50% can be modeled by single-line stuck-at 0/1 fault model. Faults extracted from two circuits are simulated with the switch-level fault simulator FMOSSIM. The test set provided by the circuits' manufacturer, which detects 100% of the single-line stuck-at 0/1 faults, detected between 73% and 89% of the simulated faults. >
248 citations
Proceedings Article•
01 Jan 1988
TL;DR: FXT as mentioned in this paper is a software tool which implements inductive fault analysis for CMOS circuits and extracts a comprehensive list of circuit-level faults for any given CMOS circuit and ranks them according to their relative likelihood of occurrence.
Abstract: FXT is a software tool which implements inductive fault analysis for CMOS circuits. It extracts a comprehensive list of circuit-level faults for any given CMOS circuit and ranks them according to their relative likelihood of occurrence. Five commercial CMOS circuits are analyzed using FXT. Of the extracted faults, approximately 50% can be modeled by single-line stuck-at 0/1 fault model. Faults extracted from two circuits are simulated with the switch-level fault simulator FMOSSIM. The test set provided by the circuits' manufacturer, which detects 100% of the single-line stuck-at 0/1 faults, detected between 73% and 89% of the simulated faults.<>
244 citations
02 Oct 1994
TL;DR: In this paper, the authors propose a comprehensive test paradigm for testing CMOS ICs that uses defect classes based on measured defect electrical properties, and describe test pattern requirements for each defect class and propose a test paradigm.
Abstract: The IC test industry has struggled for move than 30 years to establish a test approach that would guarantee a low defect level to the customer. We propose a comprehensive strategy for testing CMOS ICs that uses defect classes based on measured defect electrical properties. Defect classes differ from traditional fault models. Our defect class approach requires that the rest strategy match the defect electrical properties, while fault models require that IC defects match the fault definition. We use data from Sandia Labs failure analysis and test facilities and from public literature. We describe test pattern requirements for each defect class and propose a test paradigm.
208 citations
26 Oct 1991
TL;DR: It is found that faults caused by transistor gate-to-source and gate- to-drain shorts can be dependent not only on inputs of gates containing the faults but also on other signals.
Abstract: This paper studies the effects of shorts within CMOS gates Dynamic as well as static gate properties are analyzed as a function of the short’s resistance Increased propagation delay is found to be a common dynamic effect Circuit behavior can change drastically with small variations in a short’s resistance It is found that faults caused by transistor gate-to-source and gate-to-drain shorts can be dependent not only on inputs of gates containing the faults but also on other signals This pattern dependence due to “resistive shorts” can invalidate tests generated using normal TPG procedures
156 citations