Patent•
Configurable logic element
27 Feb 1985-
TL;DR: A configurable logic circuit achieves versatility by including a configurable combinational logic element, configurable storage circuit, and configurable output select logic as discussed by the authors, which can be configured to operate as a D flip flop, an RS latch, a transparent latch with or without set and reset inputs, or as an edge detector.
Abstract: A configurable logic circuit achieves versatility by including a configurable combinational logic element, a configurable storage circuit, and a configurable output select logic. The input signals to the configurable combinational logic element are input signals to the configurable logic circuit and feedback signals from the storage circuit. The storage circuit may be configured to operate as a D flip flop with or without set and reset inputs, an RS latch, a transparent latch with or without set and reset inputs, or as an edge detector. In conjunction with the combinational logic element, the storage circuit may also operate as a stage of a shift register or counter. The output select logic selects output signals from among the output signals of the combinational logic element and the storage circuit.
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Patent•
07 Apr 1993TL;DR: In this article, a programmable logic array integrated circuit (PLLIA) is defined, where the logic array blocks are arranged on the circuit in a two-dimensional array, and a conductor network is provided for interconnecting any logic module with any other logic module, and adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network.
Abstract: A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.
431 citations
Patent•
05 Oct 2001
TL;DR: In this article, a customizable logic array including an array of programmable cells having a multiplicity of inputs and amultiplicity of outputs and customized interconnections providing permanent direct interconnection among at least a plurality of the multiplicity inputs and at least the plurality of outputs was described.
Abstract: This invention discloses a customizable logic array including an array of programmable cells having a multiplicity of inputs and a multiplicity of outputs; and customized interconnections providing permanent direct interconnections among at least a plurality of the multiplicity of inputs and at least a plurality of the multiplicity of outputs.
425 citations
Patent•
08 Jul 1991TL;DR: In this article, a user-configurable circuit architecture includes a two-dimensional array of functional circuit modules disposed within a semiconductor substrate, and a plurality of userconfigurable interconnect elements are placed directly between the second and third interconnect layers.
Abstract: A user-configurable circuit architecture includes a two dimensional array of functional circuit modules disposed within a semiconductor substrate. A first interconnect layer disposed above and insulated from the semiconductor substrate contains a plurality of conductors and is used for internal connections within the functional circuit modules. A second interconnect layer disposed above and insulated from the first interconnect layer contains a plurality of segmented tracks of conductors running in a first direction and is used to interconnect functional circuit module inputs and outputs. A third interconnect layer disposed above and insulated from the second interconnect layer contains a plurality of segmented tracks of conductors running in a second direction, some of the segments of conductors forming intersections with ones of the segments of the conductors in the second interconnect layer, and is used to interconnect functional circuit module inputs and outputs to implement the desired applications. A plurality of user-configurable interconnect elements are placed directly between the second and third interconnect layers at the intersections of selected segments of the segmented conductors in the second and third interconnect layers. More user-configurable interconnect elements are located between adjacent segments of the segmented conductors in both the second and third interconnect layers. Pass transistors located in the semiconductor substrate in between the functional circuit modules are connected between adjacent segments in both the second and third interconnect layers and between selected intersecting segments in the second and third interconnect layers.
407 citations
Patent•
31 Jan 1994
TL;DR: The logic cell as discussed by the authors is a powerful general purpose universal logic building block suitable for implementing most TTL and gate array macrolibrary functions, including combinational logic functions as wide as thirteen inputs, all boolean transfer functions for up to three inputs, and sequential flipflop functions such as T, JK and count with carry-in.
Abstract: A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a logic cell integrated with the programmable configuration network. The logic cell includes four two-input AND gates, two six-input AND gates, three multiplexers, and a delay flipflop. The logic cell is a powerful general purpose universal logic building block suitable for implementing most TTL and gate array macrolibrary functions. A considerable variety of functions are realizable with one cell delay, including combinational logic functions as wide as thirteen inputs, all boolean transfer functions for up to three inputs, and sequential flipflop functions such as T, JK and count with carry-in.
347 citations
Patent•
06 Jun 2001TL;DR: In this paper, the authors propose to assign at least one slice of a programmable logic device (PLD) to user data memory and enable disabling access to at least N memory cells.
Abstract: A programmable logic device (PLD) comprises at least one configurable element, and a plurality of programmable logic elements for configuring the configurable element(s). Alternatively, a PLD comprises an interconnect structure and a plurality of programmable logic elements for configuring the interconnect structure. In either embodiment, at least one of the programmable logic elements includes N memory cells. A predetermined one of the N memory cells forms part of a memory slice, wherein at least a portion of each slice of the programmable logic device is allocated to either configuration data or user data memory. Typically, one memory slice provides one configuration of the programmable logic device. In accordance with one embodiment, a memory access port is coupled between at least one of the N memory cells and either one configurable element or the interconnect, thereby facilitating loading of new configuration data into other memory slices during the one configuration. The new configuration data may include off-chip or on-chip data. The present invention typically allocates at least one slice to user data memory and includes means for disabling access to at least one of the N memory cells.
294 citations
References
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17 Apr 1975TL;DR: In this paper, a memory module containing addressable memory devices, and the circuits necessary to address and drive these devices, is configured so that a trade-off between memory size and word length can be made by rewiring the backplane.
Abstract: A memory module containing addressable memory devices, and the circuits necessary to address and drive these devices, is configured so that a trade-off between memory size and word length can be made by rewiring the backplane. Thus, a single memory module design can be used for a variety of computer memory applications. This is accomplished by incorporating on the module a complete set of addressing and signal driving circuits, and allowing for the control of these module components through a system of control lines wired through the backplane.
20 citations