Conquering noise in deep-submicron digital ICs
Reads0
Chats0
TLDR
A verification metric, noise stability, which guarantees functionality in the presence of noise, and a CAD technique, static noise analysis, for applying this metric on a chipwide basis are described.Abstract:
As feature sizes decrease and clock frequencies increase, noise is becoming a greater concern in digital IC design. The authors describe a verification metric, noise stability, which guarantees functionality in the presence of noise, and a CAD technique, static noise analysis, for applying this metric on a chipwide basis.read more
Citations
More filters
Journal ArticleDOI
Soft digital signal processing
R. Hegde,Naresh R. Shanbhag +1 more
TL;DR: A prediction-based error-control scheme is proposed to enhance the performance of the filtering algorithm in the presence of errors due to soft computations, and algorithmic noise-tolerance schemes can also be used to improve theperformance of DSP algorithms in presence of bit-error rates of up to 10/sup -3/ due to deep submicron (DSM) noise.
Proceedings ArticleDOI
Probabilistic arithmetic and energy efficient embedded signal processing
TL;DR: It is shown that probabilistic arithmetic can be used to compute the FFT in an extremely energy-efficient manner, yielding energy savings of over 5.6X in the context of the widely used synthetic aperture radar (SAR) application.
Journal ArticleDOI
Harmony: static noise analysis of deep submicron digital integrated circuits
TL;DR: A metric for noise immunity is defined, and a static noise analysis methodology based on this noise-stability metric is introduced to demonstrate how noise can be analyzed systematically on a full-chip basis using simulation-based transistor-level analysis.
Proceedings ArticleDOI
Ultra-Efficient (Embedded) SOC Architectures based on Probabilistic CMOS (PCMOS) Technology
Lakshmi N. Chakrapani,Bilge E. S. Akgul,S. Cheemalavagu,Pinar Korkmaz,Krishna V. Palem,B. Seshasayee +5 more
TL;DR: This paper shows that PCMOS technology yields significant improvements, both in the energy consumed as well as in the performance, for probabilistic applications with broad utility, using an application-architecture-technology (A2T) co-design methodology introduced here.
Proceedings ArticleDOI
Design methodologies for noise in digital integrated circuits
TL;DR: The growing problems of noise in digital integrated circuits and the design tools and techniques used to ensure the noise immunity of digital designs are described.
References
More filters
Book
Analysis and Design of Analog Integrated Circuits
Paul R. Gray,Robert G. Meyer +1 more
TL;DR: In this article, the authors combine bipolar, CMOS and BiCMOS analog integrated circuits into a unified treatment that stresses their commonalities and highlights their differences, and provide valuable insights into the relative strengths and weaknesses of these important technologies.
Journal ArticleDOI
Controlled collapse reflow chip joining
TL;DR: In this paper, the authors describe a technique that prevents these solder pads from collapsing and permits large scale production by limiting the solderable area of the substrate lands and chip contact terminals so that surface tension in the molten pad and land solder supports the device until the joint solidifies.
Journal ArticleDOI
Timing analysis of computer hardware
TL;DR: This system has successfully detected all but a few timing problems for the IBM 3081 Processor Unit (consisting of almost 800 000 circuits) prior to the hardware debugging of timing.
Proceedings ArticleDOI
Noise in deep submicron digital design
TL;DR: Noise as it pertains to digital systems is defined and a metric referred to as noise stability is defined, and a static noise analysis methodology based on this metric is introduced to demonstrate how noise can be analyzed systematically.
Journal ArticleDOI
Worst-case static noise margin criteria for logic circuits and their mathematical equivalence
TL;DR: It is shown that the flip-flop approach is equivalent to an infinitely long chain with respect to the worst-case static noise margin of logic circuits, and the formal equivalence of four criteria for this worst- Case Static noise margin is demonstrated.