scispace - formally typeset
Open AccessJournal ArticleDOI

Considerations for Ultimate CMOS Scaling

K. Kuhn
- 16 May 2012 - 
- Vol. 59, Iss: 7, pp 1813-1828
Reads0
Chats0
TLDR
Transistor architectures such as extremely thin silicon-on-insulator and FinFET (and related architecture such as TriGate, Omega-FET, Pi-Gate), as well as nanowire device architectures, are compared and contrasted.
Abstract
This review paper explores considerations for ultimate CMOS transistor scaling Transistor architectures such as extremely thin silicon-on-insulator and FinFET (and related architectures such as TriGate, Omega-FET, Pi-Gate), as well as nanowire device architectures, are compared and contrasted Key technology challenges (such as advanced gate stacks, mobility, resistance, and capacitance) shared by all of the architectures will be discussed in relation to recent research results

read more

Citations
More filters
Journal ArticleDOI

A brief review of atomic layer deposition: from fundamentals to applications

TL;DR: Atomic layer deposition (ALD) is a vapor phase technique capable of producing thin films of a variety of materials as discussed by the authors, including metal oxides such as Zn1−xSnxOy, ZrO2, Y2O3, and Pt.
Journal ArticleDOI

Plasma etching: Yesterday, today, and tomorrow

TL;DR: The field of plasma etching is reviewed in this paper, where basic principles related to plasma etch such as evaporation rates and Langmuir-Hinshelwood adsorption are introduced.
Journal ArticleDOI

Scalable energy-efficient magnetoelectric spin-orbit logic.

TL;DR: A scalable spintronic logic device operating via spin–orbit transduction and magnetoelectric switching and using advanced quantum materials shows non-volatility and improved performance and energy efficiency compared with CMOS devices.
Journal ArticleDOI

The End of Moore's Law: A New Beginning for Information Technology

TL;DR: The "end of Moore's law" as discussed by the authors has been widely recognized as a major barrier to further miniaturization of semiconductor technology. But the field effect transistor is approaching some physical limits, and the associated rising costs and reduced return on investment appear to be slowing the pace of development.
Journal ArticleDOI

Brain-inspired computing with resistive switching memory (RRAM): Devices, synapses and neural networks

TL;DR: First, RRAM devices with improved window and reliability thanks to SiO x dielectric layer are discussed, then, the application of RRAM in neuromorphic computing are addressed, presenting hybrid synapses capable of spike-timing dependent plasticity (STDP).
References
More filters
Book

Operation and modeling of the MOS transistor

TL;DR: In this article, the MOS transistors with ION-IMPLANTED CHANNELS were used for CIRCUIT SIMULATION in a two-and three-tier MOS structure.
Journal ArticleDOI

Nanometre-scale electronics with III–V compound semiconductors

TL;DR: In this article, the electron transport properties of group III-V compound semiconductors have been used for the development of the first nanometre-scale logic transistors, which is the first step towards the first IC transistors.
Journal ArticleDOI

Multigate transistors as the future of classical metal–oxide–semiconductor field-effect transistors

TL;DR: In the current generation of transistors, the transistor dimensions have shrunk to such an extent that the electrical characteristics of the device can be markedly degraded, making it unlikely that the exponential decrease in transistor size can continue.
Journal ArticleDOI

Effective electron mobility in Si inversion layers in metal–oxide–semiconductor systems with a high-κ insulator: The role of remote phonon scattering

TL;DR: In this paper, the dispersion of the interfacial coupled phonon-plasmon modes, their electron-scattering strength, and their effect on the electron mobility for Si-gate structures were investigated.
Related Papers (5)