Journal ArticleDOI
Constraint-Based Layout-Driven Sizing of Analog Circuits
H. Habal,Helmut Graeb +1 more
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TLDR
A flow is presented for the automatic synthesis of an analog circuit layout based on a schematic and a list of circuit design parameter values, integrated with a deterministic nonlinear optimization algorithm to perform layout-driven circuit sizing.Abstract:
A flow is presented for the automatic synthesis of an analog circuit layout based on a schematic and a list of circuit design parameter values. The flow is driven by design, placement, and routing constraints-no layout template is necessary. Every possible layout for each device in the circuit is investigated; the layouts with the best geometric features and smallest quantization error (due to manufacturing grid alignment) are kept. For circuit placement, a complete enumeration of possible circuit placements, limited only by usual constraints of symmetry, proximity, and common centroid, is performed. Out of this enumeration a final circuit placement is selected and routed. The new flow is integrated with a deterministic nonlinear optimization algorithm to perform layout-driven circuit sizing; layouts are synthesized during both gradient approximation and next step determination. Layout-driven circuit sizing was applied to two example circuits. Sizing of the first circuit example took 8× the amount of CPU time needed for traditional circuit sizing, but remained feasible at 2.1 h of wall clock time on a contemporary workstation.read more
Citations
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Journal ArticleDOI
LAYGEN II—Automatic Layout Generation of Analog Integrated Circuits
TL;DR: The automatic layout generation is demonstrated here using the LAYGEN II tool for typical analog circuit structures, and the results in GDSII format were validated using the industrial grade verification tool Calibre®.
Journal ArticleDOI
AIDA: Layout-aware analog circuit-level sizing with in-loop layout generation
TL;DR: AIDA is presented, an analog integrated circuit design automation environment, which implements a design flow from a circuit-level specification to physical layout description, and the integration of AIDA environment on the traditional analog IC design flow is discussed, and demonstrated.
Proceedings ArticleDOI
Parasitic-aware GP-based many-objective sizing methodology for analog and RF integrated circuits
Tuotian Liao,Lihong Zhang +1 more
TL;DR: An efficient parasitic-aware geometric programming and many-objective evolution algorithm based two — phase hybrid sizing methodology is presented that has been used to optimize several analog and RF circuits in different CMOS technologies with high efficacy demonstrated.
Journal ArticleDOI
Two-Step RF IC Block Synthesis With Preoptimized Inductors and Full Layout Generation In-the-Loop
Ricardo Martins,Nuno Lourenço,Fábio Passos,Ricardo Povoa,Antonio Canelas,Elisenda Roca,Rafael Castro-Lopez,Javier Sieiro,Francisco V. Fernández,Nuno Horta +9 more
TL;DR: An analysis of the methodologies proposed in the past years to automate the synthesis of radio-frequency (RF) integrated circuit blocks is presented, and a multiobjective optimization-based layout-aware sizing approach with preoptimized integrated inductor(s) design space is proposed.
References
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Journal ArticleDOI
Matching properties of MOS transistors
TL;DR: In this paper, the matching properties of the threshold voltage, substrate factor, and current factor of MOS transistors have been analyzed and measured, and the matching results have been verified by measurements and calculations on several basic circuits.
Journal ArticleDOI
PRIMA: passive reduced-order interconnect macromodeling algorithm
TL;DR: In this article, an algorithm for generating provably passive reduced-order N-port models for linear RLC interconnect circuits is described, in which, in addition to macromodel stability, passivity is needed to guarantee the overall circuit stability.