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Journal ArticleDOI

Constructing Online Testable Circuits Using Reversible Logic

01 Jan 2010-IEEE Transactions on Instrumentation and Measurement (IEEE)-Vol. 59, Iss: 1, pp 101-109

TL;DR: A novel universal reversible logic gate (URG) and a set of basic sequential elements that could be used for building reversible sequential circuits, with 25% less garbage than the best reported in the literature are proposed.
Abstract: With the advent of nanometer technology, circuits are more prone to transient faults that can occur during its operation. Of the different types of transient faults reported in the literature, the single-event upset (SEU) is prominent. Traditional techniques such as triple-modular redundancy (TMR) consume large area and power. Reversible logic has been gaining interest in the recent past due to its less heat dissipation characteristics. This paper proposes the following: 1) a novel universal reversible logic gate (URG) and a set of basic sequential elements that could be used for building reversible sequential circuits, with 25% less garbage than the best reported in the literature; (2) a reversible gate that can mimic the functionality of a lookup table (LUT) that can be used to construct a reversible field-programmable gate array (FPGA); and (3) automatic conversion of any given reversible circuit into an online testable circuit that can detect online any single-bit errors, including soft errors in the logic blocks, using theoretically proved minimum garbage, which is significantly lesser than the best reported in the literature.
Topics: Toffoli gate (62%), Sequential logic (60%), Logic gate (59%), Flip-flop (57%), Gate array (56%)
Citations
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Journal ArticleDOI
TL;DR: The proposed sequential circuits based on conservative logic gates outperform the sequential circuits implemented in classical gates in terms of testability and a new conservative logic gate called multiplexer conservative QCA gate (MX-cqca) that is not reversible in nature but has similar properties as the Fredkin gate of working as 2:1 severalxer is presented.
Abstract: In this paper, we propose the design of two vectors testable sequential circuits based on conservative logic gates. The proposed sequential circuits based on conservative logic gates outperform the sequential circuits implemented in classical gates in terms of testability. Any sequential circuit based on conservative logic gates can be tested for classical unidirectional stuck-at faults using only two test vectors. The two test vectors are all 1's, and all 0's. The designs of two vectors testable latches, master-slave flip-flops and double edge triggered (DET) flip-flops are presented. The importance of the proposed work lies in the fact that it provides the design of reversible sequential circuits completely testable for any stuck-at fault by only two test vectors, thereby eliminating the need for any type of scan-path access to internal memory cells. The reversible design of the DET flip-flop is proposed for the first time in the literature. We also showed the application of the proposed approach toward 100% fault coverage for single missing/additional cell defect in the quantum-dot cellular automata (QCA) layout of the Fredkin gate. We are also presenting a new conservative logic gate called multiplexer conservative QCA gate (MX-cqca) that is not reversible in nature but has similar properties as the Fredkin gate of working as 2:1 multiplexer. The proposed MX-cqca gate surpasses the Fredkin gate in terms of complexity (the number of majority voters), speed, and area.

118 citations


Journal ArticleDOI
Aijiao Cui1, Yanhui Luo2, Chip-Hong Chang3Institutions (3)
TL;DR: To better resist signature attacks on scan testable cryptochip, it is proposed to fortify the key and lock method by the static obfuscation of scan data, which is unconditionally resilient against TMOSA and all other known scan-based attacks while preserving the merits of high testability and low area overhead compared with other countermeasures.
Abstract: Due to the fallibility of advanced integrated circuit (IC) fabrication processes, scan test has been widely used by cryptographic ICs to provide high fault coverage. Full controllability and observability offered by the scan design also open out the trapdoor to side-channel attacks. To better resist signature attacks on scan testable cryptochip, we propose to fortify the key and lock method by the static obfuscation of scan data. Instead of spatially reshuffling the scan cells, the working mode of some scan cells is altered to jumble up the scan data when the scan test is performed with an incorrect test key. However, when the plaintext is fed directly through the primary inputs for test efficiency, the static obfuscation of scan data is inadequate as demonstrated by a new test-mode-only signature attack (TMOSA) proposed in this paper. To thwart TMOSA, a new countermeasure based on the dynamic obfuscation of scan data is proposed. By cyclically shifting the incorrect test key throughout the test phase, the blocking cells due to the mismatched bits of the test key are made to move temporally to dynamically obfuscate the scan data. This latter scheme is unconditionally resilient against TMOSA and all other known scan-based attacks while preserving the merits of high testability and low area overhead compared with other countermeasures.

42 citations


Additional excerpts

  • ...Even if they can be identified, the extra circuitry for their identification will delay the normal inputs by several clock cycles before they can be consumed by the crypto module....

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Journal ArticleDOI
Jadav Chandra Das1, Debashis De2, Debashis De1Institutions (2)
TL;DR: The design of reversible 2 × 2 crossbar switch and its realization in Quantum-Dot Cellular Automata (QCA) for the first time is dealt with.
Abstract: Crossbar switch is an essential component in communication network like telephony and circuit switching network to process information. This paper deals with the design of reversible 2 × 2 crossbar switch and its realization in Quantum-Dot Cellular Automata (QCA) for the first time. The proposed switch is applied to a nanocommunication circuit and its impact on information processing is observed and explored. Several parameters like logic gates, density and latency are considered to evaluate the design which confirms faster operating speed and high device density. Proposed reversible QCA circuits are compared with similar traditional circuits in terms of circuit cost. The comparison outlines that the proposed QCA circuits are cost efficient than that of similar traditional circuits. The estimation of power dissipation shows that the proposed crossbar switch has very low power dissipation suitable for reversible computing. The stuck-at-fault effect on the crossbar switch and nanocommunication circuit is also explored.

34 citations


Journal ArticleDOI
Lorenzo Ciani1, Marcantonio Catelani1Institutions (1)
01 Aug 2014-Measurement
Abstract: Commercial-Off-The-Shelf (COTS) Field Programmable Gate Array (FPGA) is becoming of increase interest in many field of high-tech applications for the possibility to implement low-cost solutions with simplicity and flexibility. Nevertheless, the presence of high energy incident particles (electrons, neutrons, protons and so on) can compromise the functionality of these devices when they are used in particular environmental conditions. This is the case of avionics and space environment, where high reliability levels are necessary as project requirements and the occurrence of a fault condition, or a disturbance, cannot be ignored. To this aim the paper focuses the attention on the fault tolerant techniques for FPGA-based avionics devices in presence of radiation disturbances induced by incident particles. After a brief description of the radiation phenomenon and the effects induced on the electronic device, an evaluation of the Single Event Upset (SEU) with relative effects is carried out. Then a new fault tolerant approach is proposed in the paper in order to determine a diagnostic and correction technique. To achieve the requirements of a complex avionics system, an Integrated Control Panel for military aircraft cockpit is taken into account on this system. Several specific tests have been also carried out in order to simulate upset conditions and to prove the validity of the proposed technique.

28 citations


Proceedings ArticleDOI
05 Jan 2013-
TL;DR: Results show that the proposed design of the n-to-2n decoder is much better in terms of quantum cost, delay, hardware complexity and has significantly better scalability than the existing approach.
Abstract: This paper demonstrates the reversible logic synthesis for the n-to-2n decoder, where n is the number of data bits. The circuits are designed using only reversible fault tolerant Fredkin and Feynman double gates. Thus, the entire scheme inherently becomes fault tolerant. Algorithm for designing the generalized decoder has been presented. In addition, several lower bounds on the number of constant inputs, garbage outputs and quantum cost of the reversible fault tolerant decoder have been proposed. Transistor simulations of the proposed decoder are shown using standard p-MOS 901 and n-MOS 902 model with delay of 0.030 ns and 0.12 m channel length, which proved the functional correctness of the proposed circuits. The comparative results show that the proposed design is much better in terms of quantum cost, delay, hardware complexity and has significantly better scalability than the existing approach.

27 citations


Cites background from "Constructing Online Testable Circui..."

  • ...Over the last two decades, reversible circuitry gained remarkable interests in the field of DNA-technology [4], nano-technology [5], optical computing [6], program debugging and testing [7], quantum dot cellular automata [8], discrete event simulation [9] and in the development of highly efficient…...

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  • ...Actually, a constant complexity is assumed for each basic operation of the circuit, such as, α for Ex-OR, β for AND, γ for NOT etc....

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  • ...Hardware of digital communication systems relies heavily on decoders as it retrieve information from the coded output....

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References
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Journal ArticleDOI
TL;DR: Two simple, but representative, models of bistable devices are subjected to a more detailed analysis of switching kinetics to yield the relationship between speed and energy dissipation, and to estimate the effects of errors induced by thermal fluctuations.
Abstract: It is argued that computing machines inevitably involve devices which perform logical functions that do not have a single-valued inverse. This logical irreversibility is associated with physical irreversibility and requires a minimal heat generation, per machine cycle, typically of the order of kT for each irreversible function. This dissipation serves the purpose of standardizing signals and making them independent of their exact logical history. Two simple, but representative, models of bistable devices are subjected to a more detailed analysis of switching kinetics to yield the relationship between speed and energy dissipation, and to estimate the effects of errors induced by thermal fluctuations.

3,308 citations


Journal ArticleDOI
Charles H. Bennett1Institutions (1)
TL;DR: This result makes plausible the existence of thermodynamically reversible computers which could perform useful computations at useful speed while dissipating considerably less than kT of energy per logical step.
Abstract: The usual general-purpose computing automaton (e.g.. a Turing machine) is logically irreversible- its transition function lacks a single-valued inverse. Here it is shown that such machines may he made logically reversible at every step, while retainillg their simplicity and their ability to do general computations. This result is of great physical interest because it makes plausible the existence of thermodynamically reversible computers which could perform useful computations at useful speed while dissipating considerably less than kT of energy per logical step. In the first stage of its computation the logically reversible automaton parallels the corresponding irreversible automaton, except that it saves all intermediate results, there by avoiding the irreversible operation of erasure. The second stage consists of printing out the desired output. The third stage then reversibly disposes of all the undesired intermediate results by retracing the steps of the first stage in backward order (a process which is only possible because the first stage has been carried out reversibly), there by restoring the machine (except for the now-written output tape) to its original condition. The final machine configuration thus contains the desired output and a reconstructed copy of the input, but no other undesired data. The foregoing results are demonstrated explicitly using a type of three-tape Turing machine. The biosynthesis of messenger RNA is discussed as a physical example of reversible computation.

3,242 citations


"Constructing Online Testable Circui..." refers background in this paper

  • ...Bennett [9] showed that the kT ln 2 amount of energy dissipation would not occur if a computation is carried out in a reversible way....

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Book
01 Jan 1990-
TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Abstract: For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.

2,737 citations


"Constructing Online Testable Circui..." refers methods in this paper

  • ...Unlike manufacturing defects, the soft errors cannot be detected using conventional design-for-testability (DFT) techniques [1], although there are techniques reported in the literature, for example, the built-in soft-error resilience design paradigm [2], that reuses the existing on-chip DFT resources to reduce the soft-error rate....

    [...]


Book
01 Jan 2001-
TL;DR: Conservative logic shows that it is ideally possible to build sequential circuits with zero internal power dissipation and proves that universal computing capabilities are compatible with the reversibility and conservation constraints.
Abstract: Conservative logic is a comprehensive model of computation which explicitly reflects a number of fundamental principles of physics, such as the reversibility of the dynamical laws and the conservation of certain additive quantities (among which energy plays a distinguished role). Because it more closely mirrors physics than traditional models of computation, conservative logic is in a better position to provide indications concerning the realization of high-performance computing systems, i.e., of systems that make very efficient use of the "computing resources" actually offered by nature. In particular, conservative logic shows that it is ideally possible to build sequential circuits with zero internal power dissipation. After establishing a general framework, we discuss two specific models of computation. The first uses binary variables and is the conservative-logic counterpart of switching theory; this model proves that universal computing capabilities are compatible with the reversibility and conservation constraints. The second model, which is a refinement of the first, constitutes a substantial breakthrough in establishing a correspondence between computation and physics. In fact, this model is based on elastic collisions of identical "balls" and thus is formally identical with the atomic model that underlies the (classical) kinetic theory of perfect gases. Quite literally, the functional behavior of a general-purpose digital computer can be reproduced by a perfect gas placed in a suitably shaped container and given appropriate initial conditions.

1,810 citations


"Constructing Online Testable Circui..." refers background in this paper

  • ...This, in turn, states that the operations carried out by the devices at the particle level are reversible [11], indicating that the future computers that are to be realized using such reversible devices can be adiabatic/reversible [8], [10]....

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  • ...Direct fan-outs from the outputs of reversible gates or connecting an output of gate G directly to any input of G are not permitted while constructing circuits with reversible gates [11]....

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Journal ArticleDOI
Richard Phillips Feynman1Institutions (1)
Abstract: The physical limitations, due to quantum mechanics, on the functioning of computers are analyzed.

1,640 citations


"Constructing Online Testable Circui..." refers background in this paper

  • ...Some prominent among them are the Feynman gate [13] [Fig....

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Network Information
Related Papers (5)
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No. of citations received by the Paper in previous years
YearCitations
20213
20206
20196
20189
201719
201610