Constructing Online Testable Circuits Using Reversible Logic
TL;DR: A novel universal reversible logic gate (URG) and a set of basic sequential elements that could be used for building reversible sequential circuits, with 25% less garbage than the best reported in the literature are proposed.
Abstract: With the advent of nanometer technology, circuits are more prone to transient faults that can occur during its operation. Of the different types of transient faults reported in the literature, the single-event upset (SEU) is prominent. Traditional techniques such as triple-modular redundancy (TMR) consume large area and power. Reversible logic has been gaining interest in the recent past due to its less heat dissipation characteristics. This paper proposes the following: 1) a novel universal reversible logic gate (URG) and a set of basic sequential elements that could be used for building reversible sequential circuits, with 25% less garbage than the best reported in the literature; (2) a reversible gate that can mimic the functionality of a lookup table (LUT) that can be used to construct a reversible field-programmable gate array (FPGA); and (3) automatic conversion of any given reversible circuit into an online testable circuit that can detect online any single-bit errors, including soft errors in the logic blocks, using theoretically proved minimum garbage, which is significantly lesser than the best reported in the literature.
Citations
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TL;DR: A new cost efficient methodology of converting k -CNOT gates based circuits into respective parity preserving circuits that requires only a single wire for its formulation without an increase in number of garbage outputs and provides full fault coverage under single bit fault detection with lesser design complexity.
16 citations
TL;DR: The comparative results show that the proposed design of the FPGA is much better in terms of gate count, garbage outputs, quantum cost, delay, and hardware complexity than the existing approaches.
15 citations
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01 Jan 2014
TL;DR: This work illustrates the application of reversible logic towards testing of faults in traditional and reversible field coupled nanocircuits and proposes the design of two vectors testable sequential circuits based on conservative logic gates, which outperform the sequential circuits implemented in classical gates in terms of testability.
Abstract: Reversible computing is based on logic circuits that can generate unique output vector from each input vector, and vice versa, that is, there is a one-to-one mapping between the input and the output vectors. Reversible computing is the only solution for non-dissipative ultra low power green computing. Conservative reversible circuits are a specific type of reversible circuits, in which there would be an equal number of 1s in the outputs as there would be on the inputs, in addition to one-to-one mapping. This work illustrates the application of reversible logic towards testing of faults in traditional and reversible field coupled nanocircuits (Portions of this chapter are based on [2]. The enhancement is comprehensive treatment of: basics of reversible computing, motivation for reversible computing, background on conservative logic, basics of QCA computing, such as QCA logic devices and QCA clocking, related work etc. Several new reversible testable designs are introduced such as design of testable reversible T latch, design of testable asynchronous set/reset D latch and master-slave D flip-flop, design of testable reversible complex sequential circuits. QCA layouts of conservative logic gates are introduced with internal design details of QCA logic devices. Complete fault patterns information and analysis are provided for conservative logic gates. The synthesis of non-reversible testable design based on MX-cqca gate is extended to MX-cqca based implementation of standard functions. The significance of this work and broader prospective for future directions is also presented.). We propose the design of two vectors testable sequential circuits based on conservative logic gates. The proposed sequential circuits based on conservative logic gates outperform the sequential circuits implemented in classical gates in terms of testability. Any sequential circuit based on conservative logic gates can be tested for classical unidirectional stuck-at faults using only two test vectors. The two test vectors are all 1s, and all 0s. The designs of two vector testable latches, master-slave flip-flops, double edge triggered flip-flops, asynchronous set/reset D latch and D flip-flop are presented. The importance of the proposed work lies in the fact that it provides the design of reversible sequential circuits completely testable for any stuck-at fault by only two test vectors, thereby eliminating the need for any type of scan-path access to internal memory cells. The reversible designs of the double edge triggered flip-flop, ring counter and Johnson Counter are proposed for the first time in literature. We are showing the application of the proposed approach towards 100 % fault coverage for single missing/additional cell defect in the QCA layout of the Fredkin gate. We are also presenting a new conservative logic gate called Multiplexer Conservative QCA gate (MX-cqca) that is not reversible in nature but has similar properties as the Fredkin gate of working as 2:1 multiplexer. The proposed MX-cqca gate surpasses the Fredkin gate in terms of complexity (the number of majority voter), speed and area.
15 citations
03 Oct 2011
TL;DR: This paper alters reversible gates in such a way that they can produce information on the number of cascaded gates, and adds an appropriate reversible gate to detect missing and repeated gate faults, which can detect 100% of single and more than 97% of multiple missing/repeated gate faults.
Abstract: Reversible logic is a computation methodology with the promise of possibly zero-energy consumption by elimination of power dissipation due to information loss Furthermore, reversible logic has direct application in quantum computing However, since fault models in reversible circuits are fundamentally different from those used for CMOS VLSI technologies, therefore new testing approaches must be developed to test reversible circuits It has been shown that two new types of faults in the form of gate missing and gate repeating are more likely to occur in reversible circuits, rather than traditional stuck-at faults In this paper, we present an approach for online detection of these types of faults in reversible circuits In this approach, we modify reversible gates in such a way that they can produce information on the number of cascaded gates By using such information we add an appropriate reversible gate to detect missing and repeated gate faults Simulation results on a set of benchmark circuits confirm that the proposed approach can detect 100% of single and more than 97% of multiple missing/repeated gate faults, in average Since, the modified gates provide a combination of basic logic operation (eg NAND and NOR) in a reversible gate, therefore, using these gates effectively reduces area overhead and the number of garbage outputs, compared to previous work
15 citations
Cites background from "Constructing Online Testable Circui..."
...Variety of parity generating techniques in reversible circuits have been proposed [15], [16], [17]....
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16 Mar 2015
TL;DR: A novel design of 2:4 decoder is proposed and used to build a 3:8 decoder and a mathematical estimation of the quantum cost for n inputs decoder has been provided.
Abstract: Reversible logic has received great importance in the recent years because of its feature of reduction in power dissipation It finds applications in low power digital designs, quantum computing, nanotechnology, DNA computing etc Large number of researches are currently ongoing on sequential and combinational circuits using reversible logic Decoders are one of the most important circuits used in combinational logic Different approaches have been proposed for their design In this article, we have proposed a novel design of 2:4 decoder and have used it to build a 3:8 decoder The quantum cost for 4:16 decoder using the proposed design has been compared with a previously existing design and the design has been generalised to decoder with n inputs A mathematical estimation of the quantum cost for n inputs decoder has been provided
14 citations
Cites background or methods from "Constructing Online Testable Circui..."
...A design of 2:4 decoder using 3 Fredkin gates has been proposed in [12], as shown in Fig....
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...In this manner, 2:4 decoder can also be built [12], but the proposed design has lower quantum cost....
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References
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TL;DR: Two simple, but representative, models of bistable devices are subjected to a more detailed analysis of switching kinetics to yield the relationship between speed and energy dissipation, and to estimate the effects of errors induced by thermal fluctuations.
Abstract: It is argued that computing machines inevitably involve devices which perform logical functions that do not have a single-valued inverse. This logical irreversibility is associated with physical irreversibility and requires a minimal heat generation, per machine cycle, typically of the order of kT for each irreversible function. This dissipation serves the purpose of standardizing signals and making them independent of their exact logical history. Two simple, but representative, models of bistable devices are subjected to a more detailed analysis of switching kinetics to yield the relationship between speed and energy dissipation, and to estimate the effects of errors induced by thermal fluctuations.
3,629 citations
IBM1
TL;DR: This result makes plausible the existence of thermodynamically reversible computers which could perform useful computations at useful speed while dissipating considerably less than kT of energy per logical step.
Abstract: The usual general-purpose computing automaton (e.g.. a Turing machine) is logically irreversible- its transition function lacks a single-valued inverse. Here it is shown that such machines may he made logically reversible at every step, while retainillg their simplicity and their ability to do general computations. This result is of great physical interest because it makes plausible the existence of thermodynamically reversible computers which could perform useful computations at useful speed while dissipating considerably less than kT of energy per logical step. In the first stage of its computation the logically reversible automaton parallels the corresponding irreversible automaton, except that it saves all intermediate results, there by avoiding the irreversible operation of erasure. The second stage consists of printing out the desired output. The third stage then reversibly disposes of all the undesired intermediate results by retracing the steps of the first stage in backward order (a process which is only possible because the first stage has been carried out reversibly), there by restoring the machine (except for the now-written output tape) to its original condition. The final machine configuration thus contains the desired output and a reconstructed copy of the input, but no other undesired data. The foregoing results are demonstrated explicitly using a type of three-tape Turing machine. The biosynthesis of messenger RNA is discussed as a physical example of reversible computation.
3,497 citations
"Constructing Online Testable Circui..." refers background in this paper
...Bennett [9] showed that the kT ln 2 amount of energy dissipation would not occur if a computation is carried out in a reversible way....
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Book•
01 Jan 1990
TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Abstract: For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.
2,758 citations
"Constructing Online Testable Circui..." refers methods in this paper
...Unlike manufacturing defects, the soft errors cannot be detected using conventional design-for-testability (DFT) techniques [1], although there are techniques reported in the literature, for example, the built-in soft-error resilience design paradigm [2], that reuses the existing on-chip DFT resources to reduce the soft-error rate....
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Book•
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01 Jan 2001
TL;DR: Conservative logic shows that it is ideally possible to build sequential circuits with zero internal power dissipation and proves that universal computing capabilities are compatible with the reversibility and conservation constraints.
Abstract: Conservative logic is a comprehensive model of computation which explicitly reflects a number of fundamental principles of physics, such as the reversibility of the dynamical laws and the conservation of certain additive quantities (among which energy plays a distinguished role). Because it more closely mirrors physics than traditional models of computation, conservative logic is in a better position to provide indications concerning the realization of high-performance computing systems, i.e., of systems that make very efficient use of the "computing resources" actually offered by nature. In particular, conservative logic shows that it is ideally possible to build sequential circuits with zero internal power dissipation. After establishing a general framework, we discuss two specific models of computation. The first uses binary variables and is the conservative-logic counterpart of switching theory; this model proves that universal computing capabilities are compatible with the reversibility and conservation constraints. The second model, which is a refinement of the first, constitutes a substantial breakthrough in establishing a correspondence between computation and physics. In fact, this model is based on elastic collisions of identical "balls" and thus is formally identical with the atomic model that underlies the (classical) kinetic theory of perfect gases. Quite literally, the functional behavior of a general-purpose digital computer can be reproduced by a perfect gas placed in a suitably shaped container and given appropriate initial conditions.
1,888 citations
"Constructing Online Testable Circui..." refers background in this paper
...This, in turn, states that the operations carried out by the devices at the particle level are reversible [11], indicating that the future computers that are to be realized using such reversible devices can be adiabatic/reversible [8], [10]....
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...Direct fan-outs from the outputs of reversible gates or connecting an output of gate G directly to any input of G are not permitted while constructing circuits with reversible gates [11]....
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TL;DR: The physical limitations due to quantum mechanics on the functioning of computers are analyzed in this paper, where the physical limitations of quantum mechanics are discussed and the physical limits of quantum computing are analyzed.
Abstract: The physical limitations, due to quantum mechanics, on the functioning of computers are analyzed.
1,717 citations
"Constructing Online Testable Circui..." refers background in this paper
...Some prominent among them are the Feynman gate [13] [Fig....
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