Constructing Online Testable Circuits Using Reversible Logic
TL;DR: A novel universal reversible logic gate (URG) and a set of basic sequential elements that could be used for building reversible sequential circuits, with 25% less garbage than the best reported in the literature are proposed.
Abstract: With the advent of nanometer technology, circuits are more prone to transient faults that can occur during its operation. Of the different types of transient faults reported in the literature, the single-event upset (SEU) is prominent. Traditional techniques such as triple-modular redundancy (TMR) consume large area and power. Reversible logic has been gaining interest in the recent past due to its less heat dissipation characteristics. This paper proposes the following: 1) a novel universal reversible logic gate (URG) and a set of basic sequential elements that could be used for building reversible sequential circuits, with 25% less garbage than the best reported in the literature; (2) a reversible gate that can mimic the functionality of a lookup table (LUT) that can be used to construct a reversible field-programmable gate array (FPGA); and (3) automatic conversion of any given reversible circuit into an online testable circuit that can detect online any single-bit errors, including soft errors in the logic blocks, using theoretically proved minimum garbage, which is significantly lesser than the best reported in the literature.
Citations
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TL;DR: The proposed sequential circuits based on conservative logic gates outperform the sequential circuits implemented in classical gates in terms of testability and a new conservative logic gate called multiplexer conservative QCA gate (MX-cqca) that is not reversible in nature but has similar properties as the Fredkin gate of working as 2:1 severalxer is presented.
Abstract: In this paper, we propose the design of two vectors testable sequential circuits based on conservative logic gates. The proposed sequential circuits based on conservative logic gates outperform the sequential circuits implemented in classical gates in terms of testability. Any sequential circuit based on conservative logic gates can be tested for classical unidirectional stuck-at faults using only two test vectors. The two test vectors are all 1's, and all 0's. The designs of two vectors testable latches, master-slave flip-flops and double edge triggered (DET) flip-flops are presented. The importance of the proposed work lies in the fact that it provides the design of reversible sequential circuits completely testable for any stuck-at fault by only two test vectors, thereby eliminating the need for any type of scan-path access to internal memory cells. The reversible design of the DET flip-flop is proposed for the first time in the literature. We also showed the application of the proposed approach toward 100% fault coverage for single missing/additional cell defect in the quantum-dot cellular automata (QCA) layout of the Fredkin gate. We are also presenting a new conservative logic gate called multiplexer conservative QCA gate (MX-cqca) that is not reversible in nature but has similar properties as the Fredkin gate of working as 2:1 multiplexer. The proposed MX-cqca gate surpasses the Fredkin gate in terms of complexity (the number of majority voters), speed, and area.
130 citations
TL;DR: To better resist signature attacks on scan testable cryptochip, it is proposed to fortify the key and lock method by the static obfuscation of scan data, which is unconditionally resilient against TMOSA and all other known scan-based attacks while preserving the merits of high testability and low area overhead compared with other countermeasures.
Abstract: Due to the fallibility of advanced integrated circuit (IC) fabrication processes, scan test has been widely used by cryptographic ICs to provide high fault coverage. Full controllability and observability offered by the scan design also open out the trapdoor to side-channel attacks. To better resist signature attacks on scan testable cryptochip, we propose to fortify the key and lock method by the static obfuscation of scan data. Instead of spatially reshuffling the scan cells, the working mode of some scan cells is altered to jumble up the scan data when the scan test is performed with an incorrect test key. However, when the plaintext is fed directly through the primary inputs for test efficiency, the static obfuscation of scan data is inadequate as demonstrated by a new test-mode-only signature attack (TMOSA) proposed in this paper. To thwart TMOSA, a new countermeasure based on the dynamic obfuscation of scan data is proposed. By cyclically shifting the incorrect test key throughout the test phase, the blocking cells due to the mismatched bits of the test key are made to move temporally to dynamically obfuscate the scan data. This latter scheme is unconditionally resilient against TMOSA and all other known scan-based attacks while preserving the merits of high testability and low area overhead compared with other countermeasures.
54 citations
Additional excerpts
...Even if they can be identified, the extra circuitry for their identification will delay the normal inputs by several clock cycles before they can be consumed by the crypto module....
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TL;DR: The design of reversible 2 × 2 crossbar switch and its realization in Quantum-Dot Cellular Automata (QCA) for the first time is dealt with.
42 citations
TL;DR: Two approaches, one involving random search and the other, involving directed search have been proposed and validated on benchmark circuits considering missing-gate fault (complete and partial), bridging fault and stuck-at fault with optimum coverage and reduced computational efforts.
Abstract: Low power circuit design has been one of the major growing concerns in integrated circuit technology. Reversible circuit (RC) design is a promising future domain in computing which provides the benefit of less computational power. With the increase in the number of gates and input variables, the circuits become complex and the need for fault testing becomes crucial in ensuring high reliability of their operation. Various fault detection methods based on exhaustive test vector search approaches have been proposed in the literature. With increase in circuit complexity, a faster test generation method for providing optimal coverage becomes desirable. In this paper, a genetic algorithm-based heuristic test set generation method for fault detection in RCs is proposed which avoids the need for an exhaustive search. Two approaches, one involving random search and the other, involving directed search have been proposed and validated on benchmark circuits considering missing-gate fault (complete and partial), bridging fault and stuck-at fault with optimum coverage and reduced computational efforts.
29 citations
05 Jan 2013
TL;DR: Results show that the proposed design of the n-to-2n decoder is much better in terms of quantum cost, delay, hardware complexity and has significantly better scalability than the existing approach.
Abstract: This paper demonstrates the reversible logic synthesis for the n-to-2n decoder, where n is the number of data bits. The circuits are designed using only reversible fault tolerant Fredkin and Feynman double gates. Thus, the entire scheme inherently becomes fault tolerant. Algorithm for designing the generalized decoder has been presented. In addition, several lower bounds on the number of constant inputs, garbage outputs and quantum cost of the reversible fault tolerant decoder have been proposed. Transistor simulations of the proposed decoder are shown using standard p-MOS 901 and n-MOS 902 model with delay of 0.030 ns and 0.12 m channel length, which proved the functional correctness of the proposed circuits. The comparative results show that the proposed design is much better in terms of quantum cost, delay, hardware complexity and has significantly better scalability than the existing approach.
28 citations
Cites background from "Constructing Online Testable Circui..."
...Over the last two decades, reversible circuitry gained remarkable interests in the field of DNA-technology [4], nano-technology [5], optical computing [6], program debugging and testing [7], quantum dot cellular automata [8], discrete event simulation [9] and in the development of highly efficient…...
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...Actually, a constant complexity is assumed for each basic operation of the circuit, such as, α for Ex-OR, β for AND, γ for NOT etc....
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...Hardware of digital communication systems relies heavily on decoders as it retrieve information from the coded output....
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References
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15 Nov 2004
TL;DR: A new fault model, the missing gate fault (MGF) model, is proposed to better represent the physical failure modes of quantum technologies and it is shown that MGFs are highly testable, and that all M GFs in an N-gate k-CNOT circuit can be detected with from one to [N/2] test vectors.
Abstract: Logical reversibility occurs in low-power applications and is an essential feature of quantum circuits. Of special interest are reversible circuits constructed from a class of reversible elements called k-CNOT (controllable NOT) gates. We review the characteristics of k-CNOT circuits and observe that traditional fault models like the stuck-at model may not accurately represent their faulty behavior or test requirements. A new fault model, the missing gate fault (MGF) model, is proposed to better represent the physical failure modes of quantum technologies. It is shown that MGFs are highly testable, and that all MGFs in an N-gate k-CNOT circuit can be detected with from one to [N/2] test vectors. A design-for-test (DFT) method to make an arbitrary circuit fully testable for MGFs using a single test vector is described. Finally, we present simulation results to determine (near) optimal test sets and DFT configurations for some benchmark circuits.
107 citations
"Constructing Online Testable Circui..." refers background in this paper
...A new fault model, which is called the missing gate fault model, was proposed to represent physical failure modes of quantum technologies [27]....
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27 May 2007
TL;DR: Transistor implementation of the existing Feynman gate, Fredkin gate, Toffoli gates as well as the proposed MTG and MFG are proposed to reach towards the goal of transistor implementations of proposed reversible sequential circuits.
Abstract: This paper presents the novel designs of reversible sequential circuits (latches and flip flops). The proposed reversible latches and flip flops are designed from reversible Fredkin, Feynman and Toffoli gates. Two new reversible gates called modified Fredkin gate (MFG) and modified Toffoli gate (MTG) are also proposed to design the optimized implementations. The proposed designs are better than the recently proposed ones in terms of number of reversible gates and garbage outputs. In order to reach towards the goal of transistor implementations of proposed reversible sequential circuits, transistor implementation of the existing Feynman gate, Fredkin gate, Toffoli gates as well as the proposed MTG and MFG are also proposed. The proposed transistor implementations are completely reversible in nature, i.e., suitable for both the forward and backward computation.
98 citations
"Constructing Online Testable Circui..." refers background or methods or result in this paper
...The construction of latches and flip-flops using reversible gates is described in [23] and [32]....
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...This section presents realizations of some sequential elements that are better than those reported in [23]....
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...The construction of reversible sequential logic elements is dealt with in [23]....
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...The comparison between the proposed designs and the most recent designs reported in [23] is shown in Table I....
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...It is evident from Table I that the proposed designs lead to a 25% reduction in garbage and also a reduction in the number of 3 × 3 reversible gates, as compared with the best [23] reported in the literature....
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01 Jan 2003
TL;DR: This paper calculates the garbage required by some proposed reversible design methods and compared it to the theoretical minimum, and suggests a new reversible design method, that produces the minimum number of garbage outputs.
Abstract: In this paper we analyze the number of garbage outputs that must be added to a multiple output function to make it reversible. We give the precise formula for the theoretical minimum. For some benchmark functions, we calculate the garbage required by some proposed reversible design methods and compared it to the theoretical minimum. Based on the information about garbage we suggest a new reversible design method, that produces the minimum number of garbage outputs. Finally, we show that our proposed reversible logic structure may have some application in conventional logic design.
94 citations
"Constructing Online Testable Circui..." refers background in this paper
...Garbage is defined as the number of outputs added to make an n-input k-output Boolean function [(n, k) function] reversible [24]....
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20 May 2001
TL;DR: In this article, an accurate model of the switching mechanism of MEMS switches is presented based on a electro-mechanical analysis which takes into account the varying force and damping versus position (time).
Abstract: We present an accurate model of the switching mechanism of MEMS switches. The model is based on a electro-mechanical analysis which takes into account the varying force and damping versus position (time). The model also calculates the switching current taking into account both the capacitance change and the voltage change versus time. The model accurately predicts the switching time, the switching current, the velocity versus position (and time) of the MEMS bridge, and the energy consumed in the switching process. It is found that the current can be very large and the total switching energy is larger than predicted by simple models due to the damping underneath the MEMS bridge.
91 citations
TL;DR: In this article, a new family of logic gates for low energy computing using pulsed power CMOS logic is presented, which use the principles of adiabatic-switching and results show that in typical cases 90% of the energy can be recovered with operating frequency around 1 MHz.
Abstract: This paper presents a new family of logic gates for low energy computing using pulsed power CMOS logic. The logic gates use the principles of adiabatic-switching and results show that in typical cases 90% of the energy can be recovered with operating frequency around 1 MHz. Constant capacitance condition is enforced in our designs so that signals' energy can be efficiently recycled in the chip. We also present a detailed analysis and modeling of energy dissipation in adiabatic circuits. The models were experimentally validated using the circuit simulator SPICE. A simplified version of adiabatic logic with simplicity comparable to static CMOS circuits is also presented. For a 2/spl times/2 multiplier using this type of logic, 60% of energy can be saved over static CMOS case at 20 MHz and there is 35% less energy consumption at 100 MHz.
85 citations
"Constructing Online Testable Circui..." refers methods in this paper
...The employed power calculation method is similar to the method described in [35]....
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