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Journal ArticleDOI

Constructing Online Testable Circuits Using Reversible Logic

TL;DR: A novel universal reversible logic gate (URG) and a set of basic sequential elements that could be used for building reversible sequential circuits, with 25% less garbage than the best reported in the literature are proposed.
Abstract: With the advent of nanometer technology, circuits are more prone to transient faults that can occur during its operation. Of the different types of transient faults reported in the literature, the single-event upset (SEU) is prominent. Traditional techniques such as triple-modular redundancy (TMR) consume large area and power. Reversible logic has been gaining interest in the recent past due to its less heat dissipation characteristics. This paper proposes the following: 1) a novel universal reversible logic gate (URG) and a set of basic sequential elements that could be used for building reversible sequential circuits, with 25% less garbage than the best reported in the literature; (2) a reversible gate that can mimic the functionality of a lookup table (LUT) that can be used to construct a reversible field-programmable gate array (FPGA); and (3) automatic conversion of any given reversible circuit into an online testable circuit that can detect online any single-bit errors, including soft errors in the logic blocks, using theoretically proved minimum garbage, which is significantly lesser than the best reported in the literature.
Citations
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Journal ArticleDOI
TL;DR: The proposed sequential circuits based on conservative logic gates outperform the sequential circuits implemented in classical gates in terms of testability and a new conservative logic gate called multiplexer conservative QCA gate (MX-cqca) that is not reversible in nature but has similar properties as the Fredkin gate of working as 2:1 severalxer is presented.
Abstract: In this paper, we propose the design of two vectors testable sequential circuits based on conservative logic gates. The proposed sequential circuits based on conservative logic gates outperform the sequential circuits implemented in classical gates in terms of testability. Any sequential circuit based on conservative logic gates can be tested for classical unidirectional stuck-at faults using only two test vectors. The two test vectors are all 1's, and all 0's. The designs of two vectors testable latches, master-slave flip-flops and double edge triggered (DET) flip-flops are presented. The importance of the proposed work lies in the fact that it provides the design of reversible sequential circuits completely testable for any stuck-at fault by only two test vectors, thereby eliminating the need for any type of scan-path access to internal memory cells. The reversible design of the DET flip-flop is proposed for the first time in the literature. We also showed the application of the proposed approach toward 100% fault coverage for single missing/additional cell defect in the quantum-dot cellular automata (QCA) layout of the Fredkin gate. We are also presenting a new conservative logic gate called multiplexer conservative QCA gate (MX-cqca) that is not reversible in nature but has similar properties as the Fredkin gate of working as 2:1 multiplexer. The proposed MX-cqca gate surpasses the Fredkin gate in terms of complexity (the number of majority voters), speed, and area.

130 citations

Journal ArticleDOI
TL;DR: To better resist signature attacks on scan testable cryptochip, it is proposed to fortify the key and lock method by the static obfuscation of scan data, which is unconditionally resilient against TMOSA and all other known scan-based attacks while preserving the merits of high testability and low area overhead compared with other countermeasures.
Abstract: Due to the fallibility of advanced integrated circuit (IC) fabrication processes, scan test has been widely used by cryptographic ICs to provide high fault coverage. Full controllability and observability offered by the scan design also open out the trapdoor to side-channel attacks. To better resist signature attacks on scan testable cryptochip, we propose to fortify the key and lock method by the static obfuscation of scan data. Instead of spatially reshuffling the scan cells, the working mode of some scan cells is altered to jumble up the scan data when the scan test is performed with an incorrect test key. However, when the plaintext is fed directly through the primary inputs for test efficiency, the static obfuscation of scan data is inadequate as demonstrated by a new test-mode-only signature attack (TMOSA) proposed in this paper. To thwart TMOSA, a new countermeasure based on the dynamic obfuscation of scan data is proposed. By cyclically shifting the incorrect test key throughout the test phase, the blocking cells due to the mismatched bits of the test key are made to move temporally to dynamically obfuscate the scan data. This latter scheme is unconditionally resilient against TMOSA and all other known scan-based attacks while preserving the merits of high testability and low area overhead compared with other countermeasures.

54 citations


Additional excerpts

  • ...Even if they can be identified, the extra circuitry for their identification will delay the normal inputs by several clock cycles before they can be consumed by the crypto module....

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Journal ArticleDOI
TL;DR: The design of reversible 2 × 2 crossbar switch and its realization in Quantum-Dot Cellular Automata (QCA) for the first time is dealt with.

42 citations

Journal ArticleDOI
TL;DR: Two approaches, one involving random search and the other, involving directed search have been proposed and validated on benchmark circuits considering missing-gate fault (complete and partial), bridging fault and stuck-at fault with optimum coverage and reduced computational efforts.
Abstract: Low power circuit design has been one of the major growing concerns in integrated circuit technology. Reversible circuit (RC) design is a promising future domain in computing which provides the benefit of less computational power. With the increase in the number of gates and input variables, the circuits become complex and the need for fault testing becomes crucial in ensuring high reliability of their operation. Various fault detection methods based on exhaustive test vector search approaches have been proposed in the literature. With increase in circuit complexity, a faster test generation method for providing optimal coverage becomes desirable. In this paper, a genetic algorithm-based heuristic test set generation method for fault detection in RCs is proposed which avoids the need for an exhaustive search. Two approaches, one involving random search and the other, involving directed search have been proposed and validated on benchmark circuits considering missing-gate fault (complete and partial), bridging fault and stuck-at fault with optimum coverage and reduced computational efforts.

29 citations

Proceedings ArticleDOI
05 Jan 2013
TL;DR: Results show that the proposed design of the n-to-2n decoder is much better in terms of quantum cost, delay, hardware complexity and has significantly better scalability than the existing approach.
Abstract: This paper demonstrates the reversible logic synthesis for the n-to-2n decoder, where n is the number of data bits. The circuits are designed using only reversible fault tolerant Fredkin and Feynman double gates. Thus, the entire scheme inherently becomes fault tolerant. Algorithm for designing the generalized decoder has been presented. In addition, several lower bounds on the number of constant inputs, garbage outputs and quantum cost of the reversible fault tolerant decoder have been proposed. Transistor simulations of the proposed decoder are shown using standard p-MOS 901 and n-MOS 902 model with delay of 0.030 ns and 0.12 m channel length, which proved the functional correctness of the proposed circuits. The comparative results show that the proposed design is much better in terms of quantum cost, delay, hardware complexity and has significantly better scalability than the existing approach.

28 citations


Cites background from "Constructing Online Testable Circui..."

  • ...Over the last two decades, reversible circuitry gained remarkable interests in the field of DNA-technology [4], nano-technology [5], optical computing [6], program debugging and testing [7], quantum dot cellular automata [8], discrete event simulation [9] and in the development of highly efficient…...

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  • ...Actually, a constant complexity is assumed for each basic operation of the circuit, such as, α for Ex-OR, β for AND, γ for NOT etc....

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  • ...Hardware of digital communication systems relies heavily on decoders as it retrieve information from the coded output....

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References
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Proceedings ArticleDOI
01 Aug 2006
TL;DR: This paper proposes a set of basic sequential elements that could be used for building large reversible sequential circuits leading to logic and garbage reduction by a factor of 2 to 6 when compared to existing reversible designs reported in the literature.
Abstract: Reversible logic is gaining interest in the recent past due to its less heat dissipating characteristics. It has been proved that any Boolean function can be implemented using reversible gates. In this paper we propose a set of basic sequential elements that could be used for building large reversible sequential circuits leading to logic and garbage reduction by a factor of 2 to 6 when compared to existing reversible designs reported in the literature.

75 citations


"Constructing Online Testable Circui..." refers methods in this paper

  • ...The construction of latches and flip-flops using reversible gates is described in [23] and [ 32 ]....

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Journal ArticleDOI
TL;DR: An energy-efficient carry-lookahead adder using reversible energy recovery logic (RERL), which is a new dual-rail reversible adiabatic logic, and an eight-phase, clocked power generator that requires an off-chip inductor is described.
Abstract: In this paper, we describe an energy-efficient carry-lookahead adder using reversible energy recovery logic (RERL), which is a new dual-rail reversible adiabatic logic. We also describe an eight-phase, clocked power generator that requires an off-chip inductor. For the energy-efficient design of reversible logic, we explain how to control the overhead of reversibility with a self-energy-recovery circuit. A test chip was implemented with a 0.8 /spl mu/m CMOS technology, which included two 16-bit carry-lookahead adders to allow fair comparison: an RERL one and a static CMOS one. Experimental results showed that the RERL adder had substantial advantages in energy consumption over the static CMOS one at low operating frequencies. We also confirmed that we could minimize the energy consumption in the RERL circuit by reducing the operating frequency until adiabatic and leakage losses were equal.

71 citations


"Constructing Online Testable Circui..." refers methods in this paper

  • ...In this paper, the RERL technique described in [34] is employed for constructing the TABLE III SIMULATION RESULTS FOR THE URG SHOWN IN FIG....

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Journal ArticleDOI
TL;DR: The nMOS reversible energy recovery logic (nRERL) as discussed by the authors is a fully reversible adiabatic logic, which uses NMOS transistors only and a simpler 6-phase clocked power.
Abstract: We propose a new fully reversible adiabatic logic, nMOS reversible energy recovery logic (nRERL), which uses nMOS transistors only and a simpler 6-phase clocked power. Its area overhead and energy consumption are smaller, compared with the other fully adiabatic logics. We employed bootstrapped nMOS switches to simplify the nRERL circuits. With the simulation results for a full adder, we confirmed that the nRERL circuit consumed substantially less energy than the other adiabatic logic circuits at low-speed operation. We evaluated a test chip implemented with 0.8-/spl mu/m CMOS technology, which included a chain of nRERL inverters integrated with a clocked power generator. The nRERL inverter chain of 2400 stages consumed the minimum energy at V/sub dd/=3.5 V at 55 kHz, where the adiabatic and leakage losses are about equal, which is only 4.50% of the dissipated energy of its corresponding CMOS circuit at V/sub dd/=0.9 V. In conclusion, nRERL is more suitable than the other adiabatic logic circuits for the applications that do not require high performance but low energy consumption.

58 citations


"Constructing Online Testable Circui..." refers background in this paper

  • ...(CRL) [16], split-level CRL [17], reversible energy recovery logic (RERL) [18], [19], and NMOS RERL (nRERL) [20]....

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Proceedings ArticleDOI
04 Sep 2002
TL;DR: This paper shows how to create multipurpose reversible gates, i.e. identical reversible gates realizing simultaneously some useful functions, in synthesis of regular reversible logic circuits.
Abstract: Regular reversible logic circuits, i.e. consisting of identical reversible gates, each of which is uniformly connected to its neighbors, have small garbage. Reversible gates realizing simultaneously some useful functions are very effective in synthesis of regular reversible logic circuits. In the paper we show how to create multipurpose reversible gates. Examples of efficient binary multipurpose reversible gates are also shown.

53 citations


"Constructing Online Testable Circui..." refers background or methods in this paper

  • ...A detailed elaborate list of reversible gates reported in the literature is presented in [12]....

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  • ...A similar attempt is reported in [12], which does not realize the minimal functionally complete functions [31], namely, NAND and NOR....

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  • ...A URG, which is shown to be advantageous for synthesizing multivalued reversible logic [12], was presented....

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  • ...1(c)], the Kerntopf gate [12], and the Margolus gate [15]....

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Proceedings ArticleDOI
01 Sep 2007
TL;DR: A hybrid CNT/CMOS chemical sensor system that comprises of a carbon nanotube sensor array and a CMOS interface chip is presented, accomplished through an extensive use of CAD tools and a model-based architecture optimization.
Abstract: This paper presents an energy efficient chemical sensor system that uses carbon nanotubes (CNT) as the sensor. The room-temperature operation of CNT sensors eliminates the need for micro hot-plate arrays, which enables the low energy operation of the system. The sensor interface chip is designed in a 0.18 mum CMOS process and consumes, at maximum, 32 muW at 1.83 kS/s conversion rate. The designed interface achieves 1.34% measurement accuracy over 10 kOmega -9 MOmega dynamic range. The functionality of the full system, including CNT sensors, has been successfully demonstrated.

44 citations