Constructing Online Testable Circuits Using Reversible Logic
TL;DR: A novel universal reversible logic gate (URG) and a set of basic sequential elements that could be used for building reversible sequential circuits, with 25% less garbage than the best reported in the literature are proposed.
Abstract: With the advent of nanometer technology, circuits are more prone to transient faults that can occur during its operation. Of the different types of transient faults reported in the literature, the single-event upset (SEU) is prominent. Traditional techniques such as triple-modular redundancy (TMR) consume large area and power. Reversible logic has been gaining interest in the recent past due to its less heat dissipation characteristics. This paper proposes the following: 1) a novel universal reversible logic gate (URG) and a set of basic sequential elements that could be used for building reversible sequential circuits, with 25% less garbage than the best reported in the literature; (2) a reversible gate that can mimic the functionality of a lookup table (LUT) that can be used to construct a reversible field-programmable gate array (FPGA); and (3) automatic conversion of any given reversible circuit into an online testable circuit that can detect online any single-bit errors, including soft errors in the logic blocks, using theoretically proved minimum garbage, which is significantly lesser than the best reported in the literature.
Citations
More filters
TL;DR: The proposed sequential circuits based on conservative logic gates outperform the sequential circuits implemented in classical gates in terms of testability and a new conservative logic gate called multiplexer conservative QCA gate (MX-cqca) that is not reversible in nature but has similar properties as the Fredkin gate of working as 2:1 severalxer is presented.
Abstract: In this paper, we propose the design of two vectors testable sequential circuits based on conservative logic gates. The proposed sequential circuits based on conservative logic gates outperform the sequential circuits implemented in classical gates in terms of testability. Any sequential circuit based on conservative logic gates can be tested for classical unidirectional stuck-at faults using only two test vectors. The two test vectors are all 1's, and all 0's. The designs of two vectors testable latches, master-slave flip-flops and double edge triggered (DET) flip-flops are presented. The importance of the proposed work lies in the fact that it provides the design of reversible sequential circuits completely testable for any stuck-at fault by only two test vectors, thereby eliminating the need for any type of scan-path access to internal memory cells. The reversible design of the DET flip-flop is proposed for the first time in the literature. We also showed the application of the proposed approach toward 100% fault coverage for single missing/additional cell defect in the quantum-dot cellular automata (QCA) layout of the Fredkin gate. We are also presenting a new conservative logic gate called multiplexer conservative QCA gate (MX-cqca) that is not reversible in nature but has similar properties as the Fredkin gate of working as 2:1 multiplexer. The proposed MX-cqca gate surpasses the Fredkin gate in terms of complexity (the number of majority voters), speed, and area.
130 citations
TL;DR: To better resist signature attacks on scan testable cryptochip, it is proposed to fortify the key and lock method by the static obfuscation of scan data, which is unconditionally resilient against TMOSA and all other known scan-based attacks while preserving the merits of high testability and low area overhead compared with other countermeasures.
Abstract: Due to the fallibility of advanced integrated circuit (IC) fabrication processes, scan test has been widely used by cryptographic ICs to provide high fault coverage. Full controllability and observability offered by the scan design also open out the trapdoor to side-channel attacks. To better resist signature attacks on scan testable cryptochip, we propose to fortify the key and lock method by the static obfuscation of scan data. Instead of spatially reshuffling the scan cells, the working mode of some scan cells is altered to jumble up the scan data when the scan test is performed with an incorrect test key. However, when the plaintext is fed directly through the primary inputs for test efficiency, the static obfuscation of scan data is inadequate as demonstrated by a new test-mode-only signature attack (TMOSA) proposed in this paper. To thwart TMOSA, a new countermeasure based on the dynamic obfuscation of scan data is proposed. By cyclically shifting the incorrect test key throughout the test phase, the blocking cells due to the mismatched bits of the test key are made to move temporally to dynamically obfuscate the scan data. This latter scheme is unconditionally resilient against TMOSA and all other known scan-based attacks while preserving the merits of high testability and low area overhead compared with other countermeasures.
54 citations
Additional excerpts
...Even if they can be identified, the extra circuitry for their identification will delay the normal inputs by several clock cycles before they can be consumed by the crypto module....
[...]
TL;DR: The design of reversible 2 × 2 crossbar switch and its realization in Quantum-Dot Cellular Automata (QCA) for the first time is dealt with.
42 citations
TL;DR: Two approaches, one involving random search and the other, involving directed search have been proposed and validated on benchmark circuits considering missing-gate fault (complete and partial), bridging fault and stuck-at fault with optimum coverage and reduced computational efforts.
Abstract: Low power circuit design has been one of the major growing concerns in integrated circuit technology. Reversible circuit (RC) design is a promising future domain in computing which provides the benefit of less computational power. With the increase in the number of gates and input variables, the circuits become complex and the need for fault testing becomes crucial in ensuring high reliability of their operation. Various fault detection methods based on exhaustive test vector search approaches have been proposed in the literature. With increase in circuit complexity, a faster test generation method for providing optimal coverage becomes desirable. In this paper, a genetic algorithm-based heuristic test set generation method for fault detection in RCs is proposed which avoids the need for an exhaustive search. Two approaches, one involving random search and the other, involving directed search have been proposed and validated on benchmark circuits considering missing-gate fault (complete and partial), bridging fault and stuck-at fault with optimum coverage and reduced computational efforts.
29 citations
05 Jan 2013
TL;DR: Results show that the proposed design of the n-to-2n decoder is much better in terms of quantum cost, delay, hardware complexity and has significantly better scalability than the existing approach.
Abstract: This paper demonstrates the reversible logic synthesis for the n-to-2n decoder, where n is the number of data bits. The circuits are designed using only reversible fault tolerant Fredkin and Feynman double gates. Thus, the entire scheme inherently becomes fault tolerant. Algorithm for designing the generalized decoder has been presented. In addition, several lower bounds on the number of constant inputs, garbage outputs and quantum cost of the reversible fault tolerant decoder have been proposed. Transistor simulations of the proposed decoder are shown using standard p-MOS 901 and n-MOS 902 model with delay of 0.030 ns and 0.12 m channel length, which proved the functional correctness of the proposed circuits. The comparative results show that the proposed design is much better in terms of quantum cost, delay, hardware complexity and has significantly better scalability than the existing approach.
28 citations
Cites background from "Constructing Online Testable Circui..."
...Over the last two decades, reversible circuitry gained remarkable interests in the field of DNA-technology [4], nano-technology [5], optical computing [6], program debugging and testing [7], quantum dot cellular automata [8], discrete event simulation [9] and in the development of highly efficient…...
[...]
...Actually, a constant complexity is assumed for each basic operation of the circuit, such as, α for Ex-OR, β for AND, γ for NOT etc....
[...]
...Hardware of digital communication systems relies heavily on decoders as it retrieve information from the coded output....
[...]
References
More filters
TL;DR: In this paper, the authors proposed a reversible energy recovery logic (RERL) circuit for ultra-low energy consumption, which consumes only adiabatic energy loss and leakage current loss.
Abstract: The authors propose a reversible energy recovery logic (RERL) circuit for ultra-low-energy consumption, which consumes only adiabatic energy loss and leakage current loss by completely eliminating non-adiabatic energy loss. It is a dual-rail adiabatic circuit using the concept of reversible logic with a new eight-phase clocking scheme. Simulation results show that at low-speed operation, the RERL consumes much less energy than the complementary static CMOS circuit and other adiabatic logic circuits.
43 citations
"Constructing Online Testable Circui..." refers background in this paper
...The reversible energy recovery principles such as RERL, nRERL, etc., as mentioned in Section II, result in circuits that dissipate very less dynamic power when compared with their respective static CMOS implementations....
[...]
...In this paper, the RERL technique described in [34] is employed for constructing the reversible circuits using CMOS transmission gates....
[...]
...2 and its reversible RERL implementation....
[...]
...Many techniques for implementing the reversible circuits have been proposed until now, which include charge-recovery logic (CRL) [16], split-level CRL [17], reversible energy recovery logic (RERL) [18], [19], and NMOS RERL (nRERL) [20]....
[...]
...2) Table IV summarizes the results obtained by simulating three circuits, namely, a static CMOS implementation of a two-to-four decoder; an R1-gate-based RERL implementation of the same, as shown in Fig....
[...]
10 Oct 2004
TL;DR: Three new reversible logic gates can be used to implement reversible digital circuits of various levels of complexity and provide on-line testability for circuits implemented using them.
Abstract: A technique for an on-line testable reversible logic circuit is presented. Three new reversible logic gates have been introduced in this paper. These gates can be used to implement reversible digital circuits of various levels of complexity. The major feature of these gates is that they provide on-line testability for circuits implemented using them. The application of these gates in implementation of a subset of MCNC benchmark circuits is provided.
43 citations
"Constructing Online Testable Circui..." refers methods in this paper
...Another online testing technique for reversible logic circuits was given in [29] and [30]....
[...]
TL;DR: In this article, two different proposals for implementing reversible and dissipationless logic innanoelectronics systems are described, which use interacting single electrons housed in quantum dots to elicit logic functions.
37 citations
"Constructing Online Testable Circui..." refers background in this paper
...addition, optoelectronic and nanometer-based implementations of reversible circuits are presented in [21] and [22]....
[...]
15 Nov 2004
TL;DR: Two testable reversible logic gates can be used to implement reversible digital circuits with various levels of complexity and provide online-testability for circuits implemented using these gates.
Abstract: Two testable reversible logic gates are proposed in this paper. These gates can be used to implement reversible digital circuits with various levels of complexity. The major feature of these gates is that they provide online-testability for circuits implemented using these gates. The application of these gates in testable ripple carry, carry-skip adders and MCNC benchmark circuits have been illustrated.
30 citations
"Constructing Online Testable Circui..." refers background or methods in this paper
...The gates R1 and R2 proposed in [28]–[30] are the same....
[...]
...An online testing technique for reversible logic circuits was proposed in [28]....
[...]
01 Sep 2006
TL;DR: The authors have proposed reversible programmable logic array (RPLA) architecture using reversible Fredkin and Feynman gates and it has n inputs and m outputs and can realize m functions of n variables.
Abstract: In recent years, reversible logic has emerged as a promising computing paradigm having application in low power CMOS, quantum computing, nanotechnology, and optical computing. The classical set of gates such as AND, OR, and EXOR are not reversible. In this paper, the authors have proposed reversible programmable logic array (RPLA) architecture using reversible Fredkin and Feynman gates. The proposed RPLA has n inputs and m outputs and can realize m functions of n variables. In order to demonstrate the design of RPLA, a 3 input RPLA is designed which can perform any 28 functions using the combination of 8 min terms (23). Furthermore, the application of the designed 3 input RPLA is shown by implementing the full adder and full subtractor functions through it.
28 citations