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Journal ArticleDOI

Constructing Online Testable Circuits Using Reversible Logic

TL;DR: A novel universal reversible logic gate (URG) and a set of basic sequential elements that could be used for building reversible sequential circuits, with 25% less garbage than the best reported in the literature are proposed.
Abstract: With the advent of nanometer technology, circuits are more prone to transient faults that can occur during its operation. Of the different types of transient faults reported in the literature, the single-event upset (SEU) is prominent. Traditional techniques such as triple-modular redundancy (TMR) consume large area and power. Reversible logic has been gaining interest in the recent past due to its less heat dissipation characteristics. This paper proposes the following: 1) a novel universal reversible logic gate (URG) and a set of basic sequential elements that could be used for building reversible sequential circuits, with 25% less garbage than the best reported in the literature; (2) a reversible gate that can mimic the functionality of a lookup table (LUT) that can be used to construct a reversible field-programmable gate array (FPGA); and (3) automatic conversion of any given reversible circuit into an online testable circuit that can detect online any single-bit errors, including soft errors in the logic blocks, using theoretically proved minimum garbage, which is significantly lesser than the best reported in the literature.
Citations
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Journal ArticleDOI
TL;DR: The proposed sequential circuits based on conservative logic gates outperform the sequential circuits implemented in classical gates in terms of testability and a new conservative logic gate called multiplexer conservative QCA gate (MX-cqca) that is not reversible in nature but has similar properties as the Fredkin gate of working as 2:1 severalxer is presented.
Abstract: In this paper, we propose the design of two vectors testable sequential circuits based on conservative logic gates. The proposed sequential circuits based on conservative logic gates outperform the sequential circuits implemented in classical gates in terms of testability. Any sequential circuit based on conservative logic gates can be tested for classical unidirectional stuck-at faults using only two test vectors. The two test vectors are all 1's, and all 0's. The designs of two vectors testable latches, master-slave flip-flops and double edge triggered (DET) flip-flops are presented. The importance of the proposed work lies in the fact that it provides the design of reversible sequential circuits completely testable for any stuck-at fault by only two test vectors, thereby eliminating the need for any type of scan-path access to internal memory cells. The reversible design of the DET flip-flop is proposed for the first time in the literature. We also showed the application of the proposed approach toward 100% fault coverage for single missing/additional cell defect in the quantum-dot cellular automata (QCA) layout of the Fredkin gate. We are also presenting a new conservative logic gate called multiplexer conservative QCA gate (MX-cqca) that is not reversible in nature but has similar properties as the Fredkin gate of working as 2:1 multiplexer. The proposed MX-cqca gate surpasses the Fredkin gate in terms of complexity (the number of majority voters), speed, and area.

130 citations

Journal ArticleDOI
TL;DR: To better resist signature attacks on scan testable cryptochip, it is proposed to fortify the key and lock method by the static obfuscation of scan data, which is unconditionally resilient against TMOSA and all other known scan-based attacks while preserving the merits of high testability and low area overhead compared with other countermeasures.
Abstract: Due to the fallibility of advanced integrated circuit (IC) fabrication processes, scan test has been widely used by cryptographic ICs to provide high fault coverage. Full controllability and observability offered by the scan design also open out the trapdoor to side-channel attacks. To better resist signature attacks on scan testable cryptochip, we propose to fortify the key and lock method by the static obfuscation of scan data. Instead of spatially reshuffling the scan cells, the working mode of some scan cells is altered to jumble up the scan data when the scan test is performed with an incorrect test key. However, when the plaintext is fed directly through the primary inputs for test efficiency, the static obfuscation of scan data is inadequate as demonstrated by a new test-mode-only signature attack (TMOSA) proposed in this paper. To thwart TMOSA, a new countermeasure based on the dynamic obfuscation of scan data is proposed. By cyclically shifting the incorrect test key throughout the test phase, the blocking cells due to the mismatched bits of the test key are made to move temporally to dynamically obfuscate the scan data. This latter scheme is unconditionally resilient against TMOSA and all other known scan-based attacks while preserving the merits of high testability and low area overhead compared with other countermeasures.

54 citations


Additional excerpts

  • ...Even if they can be identified, the extra circuitry for their identification will delay the normal inputs by several clock cycles before they can be consumed by the crypto module....

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Journal ArticleDOI
TL;DR: The design of reversible 2 × 2 crossbar switch and its realization in Quantum-Dot Cellular Automata (QCA) for the first time is dealt with.

42 citations

Journal ArticleDOI
TL;DR: Two approaches, one involving random search and the other, involving directed search have been proposed and validated on benchmark circuits considering missing-gate fault (complete and partial), bridging fault and stuck-at fault with optimum coverage and reduced computational efforts.
Abstract: Low power circuit design has been one of the major growing concerns in integrated circuit technology. Reversible circuit (RC) design is a promising future domain in computing which provides the benefit of less computational power. With the increase in the number of gates and input variables, the circuits become complex and the need for fault testing becomes crucial in ensuring high reliability of their operation. Various fault detection methods based on exhaustive test vector search approaches have been proposed in the literature. With increase in circuit complexity, a faster test generation method for providing optimal coverage becomes desirable. In this paper, a genetic algorithm-based heuristic test set generation method for fault detection in RCs is proposed which avoids the need for an exhaustive search. Two approaches, one involving random search and the other, involving directed search have been proposed and validated on benchmark circuits considering missing-gate fault (complete and partial), bridging fault and stuck-at fault with optimum coverage and reduced computational efforts.

29 citations

Proceedings ArticleDOI
05 Jan 2013
TL;DR: Results show that the proposed design of the n-to-2n decoder is much better in terms of quantum cost, delay, hardware complexity and has significantly better scalability than the existing approach.
Abstract: This paper demonstrates the reversible logic synthesis for the n-to-2n decoder, where n is the number of data bits. The circuits are designed using only reversible fault tolerant Fredkin and Feynman double gates. Thus, the entire scheme inherently becomes fault tolerant. Algorithm for designing the generalized decoder has been presented. In addition, several lower bounds on the number of constant inputs, garbage outputs and quantum cost of the reversible fault tolerant decoder have been proposed. Transistor simulations of the proposed decoder are shown using standard p-MOS 901 and n-MOS 902 model with delay of 0.030 ns and 0.12 m channel length, which proved the functional correctness of the proposed circuits. The comparative results show that the proposed design is much better in terms of quantum cost, delay, hardware complexity and has significantly better scalability than the existing approach.

28 citations


Cites background from "Constructing Online Testable Circui..."

  • ...Over the last two decades, reversible circuitry gained remarkable interests in the field of DNA-technology [4], nano-technology [5], optical computing [6], program debugging and testing [7], quantum dot cellular automata [8], discrete event simulation [9] and in the development of highly efficient…...

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  • ...Actually, a constant complexity is assumed for each basic operation of the circuit, such as, α for Ex-OR, β for AND, γ for NOT etc....

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  • ...Hardware of digital communication systems relies heavily on decoders as it retrieve information from the coded output....

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References
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Journal ArticleDOI
TL;DR: It is shown that for all subsystems considered, an effective upset rate which is proportional to the product of p/sup 2/ and the time between corrections, or scrub time, can be obtained.
Abstract: The authors consider the effects of single event upsets (SEUs) on digital systems, and show techniques for designing reliable systems with current levels of SEU protection. Three main systems are discussed: main memory, logic, and cache memory. A design for the main and cache memory subsystems that are SEU protected is also described. With SEU defined in bit days p, and using single error correction, it is shown that for all subsystems considered, an effective upset rate which is proportional to the product of p/sup 2/ and the time between corrections, or scrub time, can be obtained. Data for memory chip size and performance derived from the gallium-arsenide (GaAs) pilot lines funded by the Defense Advanced Research Projects Agency (DARPA) throughout the 1980s are used. >

24 citations

Journal ArticleDOI
TL;DR: Researchers are working hard at developing one of the first reversible computers, a machine that promises to reduce energy consumption and thereby enable performance improvements in cellular telephones, laptops, and other battery-operated devices.
Abstract: Researchers are working hard at developing one of the first reversible computers, a machine that promises to reduce energy consumption and thereby enable performance improvements in cellular telephones, laptops, and other battery-operated devices. Reversible computers, also called adiabatic systems, recycle their energy and thus emit very little heat. This lets computing power grow without hitting the technology wall created by high-performance chips releasing large amounts of heat.

4 citations


"Constructing Online Testable Circui..." refers background in this paper

  • ...Reversible logic offers a lot of promises in terms of practical realization [6]....

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Proceedings ArticleDOI
Tak M. Mak1, Subhasish Mitra1, Ming Zhang1
06 Jul 2005
TL;DR: This talk demonstrates how to reuse already existent on-chip DFT resources to enable a built-in soft error resilience (BISER) design paradigm that results in more than 20 times reduction in soft error rate while incurring a system-level power overhead of 3-5%.
Abstract: In this talk, we describe a new paradigm to design in soft error resilience by reusing already existent on-chip DFT resources For example, scan systems that are required for manufacturing test and debug involve significant circuitry that are used only during post-silicon debug and production testing These resources are then left unused throughout the entire lifetime of the product as they are not required for normal system operation These structures continue to occupy additional silicon area and draw additional leakage power We demonstrate how to reuse these scan resources to enable a built-in soft error resilience (BISER) design paradigm These circuits result in more than 20 times reduction in soft error rate while incurring a system-level power overhead of 3-5% Additional power-saving techniques are possible The BISER techniques produce the best results in terms of power, performance and area overheads (when all 3 attributes are considered) compared to traditional major redundancy techniques These techniques are also suitable for adaptive applications targeting a wide range of applications (eg, networking ASICs, microprocessors) with various power, performance and soft error rate trade-offs

3 citations


"Constructing Online Testable Circui..." refers methods in this paper

  • ...Unlike manufacturing defects, the soft errors cannot be detected using conventional design-for-testability (DFT) techniques [1], although there are techniques reported in the literature, for example, the built-in soft-error resilience design paradigm [2], that reuses the existing on-chip DFT resources to reduce the soft-error rate....

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