Journal ArticleDOI
Cost-Efficient On-Chip Routing Implementations for CMP and MPSoC Systems
Samuel Rodrigo,Jose Flich,Antoni Roca,Simone Medardoni,Davide Bertozzi,Jesús Camacho,Federico Silla,José Duato +7 more
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TLDR
ULBDR is presented, an efficient logic-based mechanism that adapts to any irregular topology derived from 2-D meshes, instead of using routing tables, that requires a small set of configuration bits, thus being more practical than large routing tables implemented in memories.Abstract:
The high-performance computing domain is enriching with the inclusion of networks-on-chip (NoCs) as a key component of many-core (CMPs or MPSoCs) architectures. NoCs face the communication scalability challenge while meeting tight power, area, and latency constraints. Designers must address new challenges that were not present before. Defective components, the enhancement of application-level parallelism, or power-aware techniques may break topology regularity, thus, efficient routing becomes a challenge. This paper presents universal logic-based distributed routing (uLBDR), an efficient logic-based mechanism that adapts to any irregular topology derived from 2-D meshes, instead of using routing tables. uLBDR requires a small set of configuration bits, thus being more practical than large routing tables implemented in memories. Several implementations of uLBDR are presented highlighting the tradeoff between routing cost and coverage. The alternatives span from the previously proposed LBDR approach (with 30% of coverage) to the uLBDR mechanism achieving full coverage. This comes with a small performance cost, thus exhibiting the tradeoff between fault tolerance and performance. Power consumption, area, and delay estimates are also provided highlighting the efficiency of the mechanism. To do this, different router models (one for CMPs and one for MPSoCs) have been designed as a proof concept.read more
Citations
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Journal ArticleDOI
Scalable Hierarchical Network-on-Chip Architecture for Spiking Neural Network Hardware Implementations
Snaider Carrillo,Jim Harkin,Liam McDaid,Fearghal Morgan,Sandeep Pande,Seamus Cawley,Brian McGinley +6 more
TL;DR: A novel hierarchical network-on-chip (H-NoC) architecture for SNN hardware is presented, which aims to address the scalability issue by creating a modular array of clusters of neurons using a hierarchical structure of low and high-level routers.
Proceedings ArticleDOI
Topology-agnostic fault-tolerant NoC routing method
TL;DR: Results present the routing path for different topologies (mesh, torus, Spidergon and Hierarchical-Spidergon) in the presence of faulty routers, demonstrating that the proposed method may be adopted in NoC designs.
Proceedings ArticleDOI
Network-on-chip: Current issues and challenges
TL;DR: This tutorial shall focus on NoC routing algorithms, their implementations and issues, and discusses various turn models and how these turn model can be improved to increase adaptivity while maintaining deadlock freedom.
Proceedings ArticleDOI
A Low-Overhead, Fully-Distributed, Guaranteed-Delivery Routing Algorithm for Faulty Network-on-Chips
Mohammad Fattah,Antti Airola,Rachata Ausavarungnirun,Nima Mirzaei,Pasi Liljeberg,Juha Plosila,Siamak Mohammadi,Tapio Pahikkala,Onur Mutlu,Hannu Tenhunen +9 more
TL;DR: This paper introduces a new, practical routing algorithm, Maze-routing, to tolerate faults in network-on-chips and is the first to provide all of the following properties at the same time: fully-distributed with no centralized component, guaranteed delivery, and low area cost.
Proceedings ArticleDOI
d 2 -LBDR: Distance-driven routing to handle permanent failures in 2D mesh NoCs
TL;DR: In this article, the authors propose d2-LBDR, which adds, on every router, a distance register to the closest failure, which enables the support of more failure combinations without an excessive implementation cost.
References
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An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS
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