Current reuse triple-band signal source for multi-band wireless network-on-chip
01 Jun 2017-pp 1141-1144
TL;DR: In this paper, a triple-band signal generator is proposed which simultaneously generates a first, second, and third harmonic output signal from a 26.5-30.2 GHz fundamental voltage controlled oscillator (VCO).
Abstract: A current reuse triple-band signal generator is proposed which simultaneously generates a first, second, and third harmonic output signal from a 26.5–30.2 GHz fundamental voltage controlled oscillator (VCO). Transformer-based Gm boosting and passive 2nd harmonic extraction is proposed to achieve a good performance with exceptionally low power. A low-voltage modified Gilbert cell mixer generates the third harmonic while requiring minimal voltage overhead, facilitating an efficient current reuse topology. The fabricated signal generation circuit consumes 8 mW of power and achieves a 13% tuning range and a measured phase noise of −121 dBc/Hz at 10 MHz offset. The proposed signal source demonstrates best-in-class performance among multi-band signal sources.
Citations
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TL;DR: This brief presents a wideband millimeter-wave (mm-Wave) low noise amplifier (LNA) with a triple-coupled technique for multiband wireless applications and shows that the circuit achieves a maximum gain of 28.5 dB and a 3-dB gain bandwidth of 20 GHz with 32-mW dc power consumption.
Abstract: This brief presents a wideband millimeter-wave (mm-Wave) low noise amplifier (LNA) with a triple-coupled technique for multiband wireless applications. To enlarge the gain and reduce the supply voltage, a modified cascode topology exploiting a triple-coupled transformer is developed. Thanks to the transformer, the transconductance of the common-gate (CG) transistor of the cascode topology is also effectively boosted, and hence the gain is further increased. Furthermore, high-order networks, which are realized by combinations of $\pi $ - and T/L -type structures or transformers, are employed to implement the input, inter-stage, and output impedance matchings. They significantly broaden the bandwidth of the circuit. The LNA is demonstrated using a commercial 65-nm CMOS process. The measurement results show that the circuit achieves a maximum gain of 28.5 dB and a 3-dB gain bandwidth of 20 GHz with 32-mW dc power consumption ( $P_{dc}$ ). The measured noise figure (NF) and input 1-dB gain compression point ( $IP_{1dB}$ ) are 2.7~3.2 dB and −24.6~−20.4 dBm, respectively, over the entire operating bandwidth.
21 citations
Cites background from "Current reuse triple-band signal so..."
...As presented in [10], a transformer-based Gm-boosting topology is also proposed to implement a tripe-band signal...
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19 Oct 2017
TL;DR: This work proposes a holistic design flow that explores optimum energy and area efficient NFIC-link design as a communication backbone in a 3D manycore chip and employs statistical link analysis to select optimum NFIC link configuration.
Abstract: Near Field Inductive Coupling (NFIC) enables design of energy efficient and robust three-dimensional (3D) manycore systems. The associated design challenges and the trade-offs of the NFIC-based vertical links depend on achievable data-rates, energy and area overheads. In this work, we propose a holistic design flow that explores optimum energy and area efficient NFIC-link design as a communication backbone in a 3D manycore chip. Moreover, the design framework employs statistical link analysis to select optimum NFIC link configuration. The proposed NFIC-link design is significantly more efficient in terms of energy efficiency and area overhead compared to state-of-the-art counterpart. Energy efficiency and resiliency of NFIC-links are exploited in the context of a 3D NoC design. We demonstrate that overall reliability of the NFIC-enabled 3D NoC is significantly better compared to a conventional stand-alone TSV-based architecture.
10 citations
Cites background from "Current reuse triple-band signal so..."
...The maximum signal bandwidth is limited by self-resonance frequency (SRF) of the inductors to avoid excessive ringing in the received voltage pulse causing ISI [16]....
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...We employ decision feedback equalization (DFE) for ISI cancellation and link BER performance improvement [8]....
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...• The adverse effect of increasing inductor diameter for high data rates is inter symbol interference (ISI)....
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...zero (NRZ) data can be directly communicated using contactless channels formed by capacitive coupling or NFIC without carrier modulation [16]....
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...The major constraints in the transmitter circuits are given by: (a) the maximum peak-to-peak differential output swing, which is equal to the nominal supply voltage, and (b) the 20%–80% transition time of the serialization and driver circuits that is limited to one-third of a bit period to avoid excessive ISI [19][20]....
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TL;DR: An inductorless wideband gain-boosted baseband (BB) amplifier suitable for wireless network-on-chip (WiNoC) architectures and achieves the best figure of merit among existing amplifiers in similar CMOS technology nodes is presented.
Abstract: This paper presents an inductorless wideband gain-boosted baseband (BB) amplifier suitable for wireless network-on-chip (WiNoC) architectures. Current reuse active feedback (FB) and feed-forward (FF) techniques are proposed for extending bandwidth, increasing gain, and reducing power consumption and area overhead compared to traditional BB amplifiers. To maximize the benefits of the FB and FF amplifiers, a skewed differential topology is introduced, which reduces the impact of ringing in the amplifier’s step response, allowing greater design flexibility and improved performance. The amplifier is fabricated in 65-nm CMOS and achieves a bandwidth of 11 GHz with a small active area, 0.0029 mm2, due to the inductorless bandwidth-extension technique. The amplifier consumes 2.58 mW from a 1-V supply, suitable for a high-data-rate wireless receiver in power- and area-constrained WiNoC. With the proposed BB amplifier, a 60-GHz ON–OFF-keying (OOK) receiver for WiNoC is presented to demonstrate excellent energy efficiency and compact area. The wireless receiver demodulates 16-Gb/s OOK while consuming 16.3 mA with a small area overhead of 0.09 mm2. Based on the high bandwidth, low-power consumption, and small area overhead, to the best of the author’s knowledge, the amplifier achieves the best figure of merit among existing amplifiers in similar CMOS technology nodes.
8 citations
Cites background from "Current reuse triple-band signal so..."
...Recent advances in mm-wave wireless transceivers in CMOS [2], [7]–[10], [14]–[22] and the high fT of modern scaled CMOS processes have enabled the design of suitable transceiver circuits....
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...Wireless NoC (WiNoC) [2], [7]–[21] is an emerging technology which enables single-hop cross-chip links using wireless interconnects....
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TL;DR: This work presents a wireless-wireline hybrid 3D interconnect that employs orthogonal simultaneous bidirectional signaling for 3D Network-on-chip to achieve $2\times $ bandwidth density and demonstrates on how equalization has the potential to decouple the fundamental energy-area tradeoff.
Abstract: For the first time, this work presents a wireless-wireline hybrid 3D interconnect that employs orthogonal simultaneous bidirectional signaling for 3D Network-on-chip to achieve $2\times $ bandwidth density. We combine wireless near-field inductive coupling channel (NFIC) encompassing wireline through-silicon vias (TSV) to leverage orthogonal simultaneous bidirectional (SBD) signaling. This technique provides an efficient way of doubling interconnect bandwidth in the same area by means of passive wireless and wireline interconnects. The proposed hybrid 3D interconnect shows at least -70dB of NFIC-TSV isolation in the band of interest. We also present a comprehensive link analysis to derive the energy-area trade-off of an NFIC link and its fundamental performance limits. Further, we demonstrate on how equalization has the potential to decouple the fundamental energy-area tradeoff. The prototype transceiver measures a simultaneous bidirectional data and clock communication at an effective data rate of 6.6 Gb/s consuming 263 fJ/bit in 65 nm CMOS bulk process. The developed hybrid 3D interconnect architecture exhibits a $2\times $ improved link performance over state-of-the-art 3D simultaneous bidirectional links. A hybrid 3D Network-on-chip (3D NoC) implementation is demonstrated using the proposed hybrid interconnect technology and shows a 50% lower area and cost for the same energy-delay-product (EDP) over the conventional TSV based links.
8 citations
Cites background from "Current reuse triple-band signal so..."
...On-chip frequency modulation has been proposed in [17] to increase data rates by using multiple frequency bands, which, however, comes at the cost of power- and area-inefficient mixers and oscillators [23]....
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...The increased bandwidth density is achieved by combining the benefits of complementary face-to-back 3D integration technologies: wireline-TSV and wireless-NFIC without any carrier modulation [23], [24], [31]....
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TL;DR: The proposed design framework employs statistical link analysis to select optimum NFIC-link configuration and is significantly more efficient in terms of energy efficiency and area overhead compared to the state-of-the-art counterparts.
Abstract: Wireless interconnects using near-field inductive coupling (NFIC) enables contactless vertical communications necessary for the design of energy efficient and robust 3-D manycore systems. However, the achievable performance, energy efficiency, bandwidth, and associated area overhead of NFICs are intertwined imposing significant design challenges and tradeoffs to explore the optimum link configuration. To address these challenges, in this paper, we propose a holistic design approach for exploring energy-efficient NFICs and target to exploit the benefits of the NFICs in the context of efficient and reliable network-on-chip (NoC) design. The proposed design framework employs statistical link analysis to select optimum NFIC-link configuration and is significantly more efficient in terms of energy efficiency and area overhead compared to the state-of-the-art counterparts. We demonstrate that 3-D NoCs incorporating NFIC-enabled links outperform through-silicon-via (TSV) counterparts. In addition, the overall reliability of TSV- and NFIC-enabled hybrid 3-D NoC is significantly better than only TSV-based NoCs in order to counteract the electromigration and workload-induced stress challenges.
7 citations
Cites background from "Current reuse triple-band signal so..."
...Chip-to-chip data transmission in nonreturn-to-zero (NRZ) format can be directly accomplished using wireless channels formed by CC or NFIC without any carrier modulation for vertical communication [1], [29], [30]....
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TL;DR: In this article, a transformer-feedback voltage-controlled oscillator (TF-VCO) is proposed to achieve low-phase-noise and low-power designs even at a supply below the threshold voltage.
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309 citations
"Current reuse triple-band signal so..." refers methods in this paper
...Furthermore, this transformer Gm boosting results in an impulse sensitivity function (ISF) similar to that of a Colpitt’s oscillator, improving the phase noise performance [4]....
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TL;DR: Both experimental and analysis results show that the NoC architecture scales very well in terms of area, performance, energy, and design effort, while the P2P and bus-based architectures scale poorly on all accounts except for performance and area, respectively.
Abstract: Traditionally, design-space exploration for systems-on-chip (SoCs) has focused on the computational aspects of the problem at hand. However, as the number of components on a single chip and their performance continue to increase, a shift from computation-based to communication-based design becomes mandatory. As a result, the communication architecture plays a major role in the area, performance, and energy consumption of the overall system. This article presents a comprehensive evaluation of three on-chip communication architectures targeting multimedia applications. Specifically, we compare and contrast the network-on-chip (NoC) with point-to-point (P2P) and bus-based communication architectures in terms of area, performance, and energy consumption. As the main contribution, we present complete P2P, bus-, and NoC-based implementations of a real multimedia application (i. e. the MPEG-2 encoder), and provide direct measurements using an FPGA prototype and actual video clips, rather than simulation and synthetic workloads. We also support the experimental findings through a theoretical analysis. Both experimental and analysis results show that the NoC architecture scales very well in terms of area, performance, energy, and design effort, while the P2P and bus-based architectures scale poorly on all accounts except for performance and area, respectively.
228 citations
TL;DR: The proposed mm-wave wireless NoC (mWNoC) outperforms the corresponding conventional wireline counterpart in terms of achievable bandwidth and is significantly more energy efficient.
Abstract: The Network-on-chip (NoC) is an enabling technology to integrate large numbers of embedded cores on a single die. The existing methods of implementing a NoC with planar metal interconnects are deficient due to high latency and significant power consumption arising out of multihop links used in data exchange. To address these problems, we propose design of a hierarchical small-world wireless NoC architecture where the multihop wire interconnects are replaced with high-bandwidth and single-hop long-range wireless shortcuts operating in the millimeter (mm)-wave frequency range. The proposed mm-wave wireless NoC (mWNoC) outperforms the corresponding conventional wireline counterpart in terms of achievable bandwidth and is significantly more energy efficient. The performance improvement is achieved through efficient data routing and optimum placement of wireless hubs. Multiple wireless shortcuts operating simultaneously further enhance the performance, and provide an energy-efficient solution for design of communication infrastructures for multicore chips.
189 citations
"Current reuse triple-band signal so..." refers background in this paper
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TL;DR: In this paper, the AM-to-PM noise conversion due to varactors and nonlinear capacitances is discussed and a rigorous approach to the quantitative estimate of the conversion factor and a closed-form expression is derived.
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95 citations
"Current reuse triple-band signal so..." refers background in this paper
...The peak visible between 3 and 4 MHz on the fundamental trace is a result of noise from the power supply modulating the analog varactor [6]....
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