Appears in the Proceedings of the 38
th
International Symposium on Computer Architecture (ISCA ’11)
Dark Silicon and the End of Multicore Scaling
Hadi Esmaeilzadeh
†
Emily Blem
‡
Renée St. Amant
§
Karthikeyan Sankaralingam
‡
Doug Burger
†
University of Washington
‡
University of Wisconsin-Madison
§
The University of Texas at Austin
Microsoft Research
hadianeh@cs.washington.edu blem@cs.wisc.edu stamant@cs.utexas.edu karu@cs.wisc.edu dburger@microsoft.com
ABSTRACT
Since 2005, processor designers have increased core counts to ex-
ploit Moore’s Law scaling, rather than focusing on single-core per-
formance. The failure of Dennard scaling, to which the shift to mul-
ticore parts is partially a response, may soon limit multicore scaling
just as single-core scaling has been curtailed. This paper models
multicore scaling limits by combining device scaling, single-core
scaling, and multicore scaling to measure the speedup potential for
a set of parallel workloads for the next five technology generations.
For device scaling, we use both the ITRS projections and a set
of more conservative device scaling parameters. To model single-
core scaling, we combine measurements from over 150 processors
to derive Pareto-optimal frontiers for area/performance and pow-
er/performance. Finally, to model multicore scaling, we build a de-
tailed performance model of upper-bound performance and lower-
bound core power. The multicore designs we study include single-
threaded CPU-like and massively threaded GPU-like multicore chip
organizations with symmetric, asymmetric, dynamic, and composed
topologies. The study shows that regardless of chip organization
and topology, multicore scaling is power limited to a degree not
widely appreciated by the computing community. Even at 22 nm
(just one year from now), 21% of a fixed-size chip must be powered
off, and at 8 nm, this number grows to more than 50%. Through
2024, only 7.9×average speedup is possible across commonly used
parallel workloads, leaving a nearly 24-fold gap from a target of
doubled performance per generation.
Categories and Subject Descriptors: C.0 [Computer Systems Or-
ganization] General — Modeling of computer architecture; C.0
[Computer Systems Organization] General — System architectures
General Terms: Design, Measurement, Performance
Keywords: Dark Silicon, Modeling, Power, Technology Scaling,
Multicore
1. INTRODUCTION
Moore’s Law [23] (the doubling of transistors on chip every 18
months) has been a fundamental driver of computing. For the past
three decades, through device, circuit, microarchitecture, architec-
Permission to make digital or hard copies of all or part of this work for
personal or classroom use is granted without fee provided that copies are
not made or distributed for profit or commercial advantage and that copies
bear this notice and the full citation on the first page. To copy otherwise, to
republish, to post on servers or to redistribute to lists, requires prior specific
permission and/or a fee.
ISCA’11, June 4–8, 2011, San Jose, California, USA.
Copyright 2011 ACM 978-1-4503-0472-6/11/06 ...$10.00.
ture, and compiler advances, Moore’s Law, coupled with Dennard
scaling [11], has resulted in commensurate exponential performance
increases. The recent shift to multicore designs has aimed to in-
crease the number of cores along with transistor count increases,
and continue the proportional scaling of performance. As a re-
sult, architecture researchers have started focusing on 100-core and
1000-core chips and related research topics and called for changes
to the undergraduate curriculum to solve the parallel programming
challenge for multicore designs at these scales.
With the failure of Dennard scaling–and thus slowed supply volt-
age scaling–core count scaling may be in jeopardy, which would
leave the community with no clear scaling path to exploit contin-
ued transistor count increases. Since future designs will be power
limited, higher core counts must provide performance gains despite
the worsening energy and speed scaling of transistors, and given
the available parallelism in applications. By studying these charac-
teristics together, it is possible to predict for how many additional
technology generations multicore scaling will provide a clear ben-
efit. Since the energy efficiency of devices is not scaling along with
integration capacity, and since few applications (even from emerg-
ing domains such as recognition, mining, and synthesis [5]) have
parallelism levels that can efficiently use a 100-core or 1000-core
chip, it is critical to understand how good multicore performance
will be in the long term. In 2024, will processors have 32 times the
performance of processors from 2008, exploiting five generations
of core doubling?
Such a study must consider devices, core microarchitectures,
chip organizations, and benchmark characteristics, applying area
and power limits at each technology node. This paper consid-
ers all those factors together, projecting upper-bound performance
achievable through multicore scaling, and measuring the effects of
non-ideal device scaling, including the percentage of “dark silicon”
(transistor under-utilization) on future multicore chips. Additional
projections include best core organization, best chip-level topology,
and optimal number of cores.
We consider technology scaling projections, single-core design
scaling, multicore design choices, actual application behavior, and
microarchitectural features together. Previous studies have also
analyzed these features in various combinations, but not all to-
gether [8, 9, 10, 14, 15, 20, 22, 27, 28]. This study builds and
combines three models to project performance and fraction of “dark
silicon” on fixed-size and fixed-power chips as listed below:
• Device scaling model (DevM): area, frequency, and power
requirements at future technology nodes through 2024.
• Core scaling model (CorM): power/performance and area/
performance single core Pareto frontiers derived from a large
set of diverse microprocessor designs.
• Multicore scaling model (CmpM): area, power and perfor-
Figure 1: Overview of the models and the methodology
mance of any application for “any” chip topology for CPU-
like and GPU-like multicore performance.
• DevM ×CorM: Pareto frontiers at future technology nodes;
any performance improvements for future cores will come
only at the cost of area or power as defined by these curves.
• CmpM×DevM×CorM and an exhaustive state-space search:
maximum multicore speedups for future technology nodes
while enforcing area, power, and benchmark constraints.
The results from this study provide detailed best-case multicore
performance speedups for future technologies considering real ap-
plications from the PARSEC benchmark suite [5]. Our results eval-
uating the PARSEC benchmarks and our upper-bound analysis con-
firm the following intuitive arguments:
i) Contrary to conventional wisdom on performance improve-
ments from using multicores, over five technology generations, only
7.9× average speedup is possible using ITRS scaling.
ii) While transistor dimensions continue scaling, power limita-
tions curtail the usable chip fraction. At 22 nm (i.e. in 2012), 21%
of the chip will be dark and at 8 nm, over 50% of the chip will not
be utilized using ITRS scaling.
iii) Neither CPU-like nor GPU-like multicore designs are suffi-
cient to achieve the expected performance speedup levels. Radical
microarchitectural innovations are necessary to alter the power/per-
formance Pareto frontier to deliver speed-ups commensurate with
Moore’s Law.
2. OVERVIEW
Figure 1 shows how this paper combines models and empirical
measurements to project multicore performance and chip utiliza-
tion. There are three components used in our approach:
Device scaling model (DevM): We build a device-scaling model
that provides the area, power, and frequency scaling factors at tech-
nology nodes from 45 nm to 8 nm. We consider ITRS Roadmap
projections [18] and conservative scaling parameters from Borkar’s
recent study [7].
Core scaling model (CorM): The core-level model provides the
maximum performance that a single-core can sustain for any given
area. Further, it provides the minimum power (or energy) that must
be consumed to sustain this level of performance. To quantify, we
measure the core performance in terms of SPECmark. We consider
empirical data from a large set of processors and use curve fitting
to obtain the Pareto-optimal frontiers for single-core area/perfor-
mance and power/performance tradeoffs.
Multicore scaling model (CmpM): We model two mainstream
classes of multicore organizations, multi-core CPUs and many-thread
GPUs, which represent two extreme points in the threads-per-core
spectrum. The CPU multicore organization represents Intel Nehalem-
like, heavy-weight multicore designs with fast caches and high single-
thread performance. The GPU multicore organization represents
NVIDIA Tesla-like lightweight cores with heavy multithreading
support and poor single-thread performance. For each multicore
organization, we consider four topologies: symmetric, asymmet-
ric, dynamic, and composed (also called “fused” in the literature).
Symmetric Multicore: The symmetric, or homogeneous, multicore
topology consists of multiple copies of the same core operating at
the same voltage and frequency setting. In a symmetric multicore,
the resources, including the power and the area budget, are shared
equally across all cores.
Asymmetric Multicore: The asymmetric multicore topology con-
sists of one large monolithic core and many identical small cores.
The design leverages the high-performing large core for the serial
portion of code and leverages the numerous small cores as well as
the large core to exploit the parallel portion of code.
Dynamic Multicore: The dynamic multicore topology is a varia-
tion of the asymmetric multicore topology. During parallel code
portions, the large core is shut down and, conversely, during the
serial portion, the small cores are turned off and the code runs only
on the large core [8, 26].
Composed Multicore: The composed multicore topology consists
of a collection of small cores that can logically fuse together to
compose a high-performance large core for the execution of the
serial portion of code [17, 19]. In either serial or parallel cases, the
large core or the small cores are used exclusively.
Table 1 outlines the design space we explore and explains the
roles of the cores during serial and parallel portions of applica-
Table 1: CPU and GPU topologies (ST Core: Single-Thread Core and MT: Many-Thread Core)
Symmetric Asymmetric Dynamic Composed
CPU Serial 1 ST Core 1 Large ST Core 1 Large ST Core 1 Large ST Core
Multicores Parallel N ST Cores 1 Large ST Core + N Small ST Cores N Small ST Cores N Small ST Cores
Serial
1 MT Core 1 Large ST Core 1 Large ST Core 1 Large ST Core
GPU (1 Thread) (1 Thread) (1 Thread) (1 Thread)
Multicores
Parallel
N MT Cores 1 Large ST Core + N Small MT Cores N Small MT Cores N Small MT Cores
(Multiple Threads) (1 Thread) (Multiple Threads) (Multiple Threads) (Multiple Threads)
Table 2: Scaling factors for ITRS and Conservative projections.
Frequency Vdd Capacitance Power
Tech Scaling Scaling Scaling Scaling
Node Factor Factor Factor Factor
Year (nm) (/45nm) (/45nm) (/45nm) (/45nm)
ITRS
2010 45
∗
1.00 1.00 1.00 1.00
2012 32
∗
1.09 0.93 0.7 0.66
2015 22
†
2.38 0.84 0.33 0.54
2018 16
†
3.21 0.75 0.21 0.38
2021 11
†
4.17 0.68 0.13 0.25
2024 8
†
3.85 0.62 0.08 0.12
31% frequency increase and 35% power reduction per node
Conservative
2008 45 1.00 1.00 1.00 1.00
2010 32 1.10 0.93 0.75 0.71
2012 22 1.19 0.88 0.56 0.52
2014 16 1.25 0.86 0.42 0.39
2016 11 1.30 0.84 0.32 0.29
2018 8 1.34 0.84 0.24 0.22
6% frequency increase and 23% power reduction per node
∗: Extended Planar Bulk Transistors, †:Multi-Gate Transistors
tions. Single-thread (ST) cores are uni-processor style cores with
large caches and many-thread (MT) cores are GPU-style cores with
smaller caches; both are described in more detail in Section 5.
This paper describes an analytic model that provides system-
level performance using as input the core’s performance (obtained
from CorM) and the multicore’s organization (CPU-like or GPU-
like). Unlike previous studies, the model considers application
behavior, its memory access pattern, the amount of thread-level
parallelism in the workload, and microarchitectural features such
as cache size, memory bandwidth, etc. We choose the PARSEC
benchmarks because they represent a set of highly parallel applica-
tions that are widely studied in the research community.
Heterogeneous configurations such as AMD Fusion and Intel
Sandybrige combine CPU and GPU designs on a single chip. The
asymmetric and dynamic GPU topologies resemble those two de-
signs, and the composed topology models configurations similar to
AMD Bulldozer. For GPU-like multicores, this study assumes that
the single ST core does not participate in parallel work. Finally,
our methodology implicitly models heterogeneous cores of differ-
ent types (mix of issue widths, frequencies, etc.) integrated on one
chip. Since we perform a per-benchmark optimal search for each
organization and topology, we implicitly cover the upper-bound of
this heterogeneous case.
3. DEVICE MODEL
We consider two different technology scaling schemes to build a
device scaling model. The first scheme uses projections from the
ITRS 2010 technology roadmap [18]. The second scheme, which
we call conservative scaling, is based on predictions presented by
Borkar and represents a less optimistic view [7]. The parameters
used for calculating the power and performance scaling factors are
summarized in Table 2. For ITRS scaling, frequency is assumed to
scale linearly with respect to FO4 inverter delay. The power scaling
factor is computed using the predicted frequency, voltage, and gate
capacitance scaling factors in accordance with the P = αCV
2
dd
f
equation. The ITRS roadmap predicts that multi-gate MOSFETs,
such as FinTETs, will supersede planar bulk at 22 nm [18]. Table 2
also highlights the key difference between the two projections. De-
tails on how we handle the partitioning between leakage power and
dynamic power is explained in Section 4.2.
4. CORE MODEL
This paper uses Pareto frontiers to provide single-core power/per-
formance and area/performance tradeoffs at each technology node
while abstracting away specific details of the cores. The Pareto-
optimal core model provides two functions, A(q) and P(q), repre-
senting the area/performance and power/performance tradeoff Pareto
frontiers, where q is the single-threaded performance of a core
measured in SPECmarks. These functions are derived from the
data collected for a large set of processors. The power/perfor-
mance Pareto frontier represents the optimal design points in terms
of power and performance [16]. Similarly, the area/performance
Pareto frontier represents the optimal design points in the area/per-
formance design space. Below, we first describe why separate area
and power functions are required. Then, we describe the basic
model and empirical data used to derive the actual Pareto frontier
curves at 45 nm. Finally, we project these power and area Pareto
frontiers to future technology nodes using the device scaling model.
4.1 Decoupling Area and Power Constraints
Previous studies on multicore performance modeling [8, 9, 10,
15, 20, 22, 28] use Pollack’s rule [6] to denote the tradeoff be-
tween transistor count and performance. Furthermore, these stud-
ies consider the power consumption of a core to be directly propor-
tional to its transistor count. This assumption makes power an area-
dependent constraint. However, power is a function of not only
area, but also supply voltage and frequency. Since these no longer
scale at historical rates, Pollack’s rule is insufficient for modeling
core power. Thus, it is necessary to decouple area and power into
two independent constraints.
4.2 Pareto Frontier Derivation
Figure 2(a) shows the power/performance single-core design space.
We populated the depicted design space by collecting data for 152
real processors (from P54C Pentium to Nehalem-based i7) fabri-
cated at various technology nodes from 600 nm through 45 nm.
As shown, the boundary of the design space that comprises the
power/performance optimal points constructs the Pareto frontier.
Each processor’s performance is collected from the SPEC website
[25] and the processor’s power is the TDP reported in its datasheet.
Thermal design power, TDP, is the chip power budget, the amount
of power the chip can dissipate without exceeding transistors junc-
tion temperature. In Figure 2(a), the x-axis is the SPEC CPU2006 [25]
0 5 10 15 20 25 30 35 40
Performance (SP ECmark)
0
10
20
30
40
50
60
70
80
90
Core Power (W )
Processors (600 nm)
Processors (350 nm)
Processors (250 nm)
Processors (180 nm)
Processors (130 nm)
Processors (90 nm)
Processors (65 nm)
Processors (45 nm)
Pareto Frontier (45 nm)
(a) Power/performance across nodes
0 5 10 15 20 25 30 35 40
Performance (SP ECmark)
0
5
10
15
20
25
30
Core Power (W )
P (q) = 0.0002q
3
+ 0.0009q
2
+ 0.3859q − 0.0301
Intel Nehalem (45nm)
Intel Core (45nm)
AMD Shanghai (45nm)
Intel Atom (45nm)
Pareto Frontier (45 nm)
(b) Power/performance frontier, 45 nm
0 5 10 15 20 25 30 35 40
Performance (SP ECmark)
5
10
15
20
25
30
Core Area (mm
2
)
A(q) = 0.0152q
2
+ 0.0265q + 7.4393
Intel Nehalem (45nm)
Intel Core (45nm)
AMD Shanghai (45nm)
Intel Atom (45nm)
Pareto Frontier (45 nm)
(c) Area/performance frontier, 45 nm
0 5 10 15 20 25 30 35 40
Performance (SPECmark)
0
5
10
15
20
25
Core Power (W )
Voltage Scaling
Frequency Scaling
Pareto Frontier (45 nm)
(d) Voltage and frequency scaling
0 20 40 60 80 100 120 140 160
Performance (SPECmark)
0
5
10
15
20
25
Core Power (W )
45 nm
32 nm
22 nm
16 nm
11 nm
8 nm
(e) ITRS frontier scaling
0 10 20 30 40 50
Performance (SPECmark)
0
5
10
15
20
25
Core Power (W )
45 nm
32 nm
22 nm
16 nm
11 nm
8 nm
(f) Conservative frontier scaling
Figure 2: Deriving the area/performance and power/performance Pareto frontiers
score (SPECmark) of the processor, and the y-axis is the core power
budget. All SPEC scores are converted to SPEC CPU2006 scores.
Empirical data for the core model: To build a technology-scalable
model, we consider a family of processors at one technology node
(45 nm) and construct the frontier for that technology node. We
used 20 representative Intel and AMD processors at 45 nm (Atom
Z520, Atom 230, Atom D510, C2Duo T9500, C2Extreme QX9650,
C2Q-Q8400, Opteron 2393SE, Opteron 2381HE, C2Duo E7600,
C2Duo E8600, C2Quad Q9650, C2Quad QX9770, C2Duo T9900,
Pentium SU2700, Xeon E5405, Xeon E5205, Xeon X3440, Xeon
E7450, i7-965 ExEd). The power/performance design space and
the cubic Pareto frontier at 45 nm, P(q), are depicted in Figure 2(b).
To derive the quadratic area/performance Pareto frontier (Fig-
ure 2(c)), die photos of four microarchitectures, including Intel
Atom, Intel Core, AMD Shanghai, and Intel Nehalem, are used
to estimate the core areas (excluding level 2 and level 3 caches).
The Intel Atom Z520 with a 2.2 W total TDP represents the lowest
power design (lower-left frontier point), and the Nehalem-based
Intel Core i7-965 Extreme Edition with a 130 W total TDP rep-
resents the highest performing (upper-right frontier point). Other
low-power architectures, such as those from ARM and Tilera, were
not included because their SPECmark were not available for a mean-
ingful performance comparison.
Since the focus of this work is to study the impact of power con-
straints on logic scaling rather than cache scaling, we derive the
Pareto frontiers using only the portion of chip power budget (TDP)
allocated to each core. To compute the power budget of a single
core, the power budget allocated to the level 2 and level 3 caches
is estimated and deducted from the chip TDP. In the case of a mul-
ticore CPU, the remainder of the chip power budget is divided by
the number of cores, resulting in the power budget allocated to a
single core (1.89 W for the Atom core in Z520 and 31.25 W for
each Nehalem core in i7-965 Extreme Edition). We allocate 20%
of the chip power budget to leakage power. As shown in [24], the
transistor threshold voltage can be selected so that the maximum
leakage power is always an acceptable ratio of the chip power bud-
get while still meeting the power and performance constraints. We
also observe that with 10% or 30% leakage power, we do not see
significant changes in optimal configurations.
Deriving the core model: To derive the Pareto frontiers at 45 nm,
we fit a cubic polynomial, P(q), to the points along the edge of the
power/performance design space. We fit a quadratic polynomial
(Pollack’s rule), A(q), to the points along the edge of the area/per-
formance design space. We used the least square regression method
for curve fitting such that the frontiers enclose all design points.
Figures 2(b) and 2(c) show the 45 nm processor points and identify
the power/performance and area/performance Pareto frontiers. The
power/performance cubic polynomial P(q) function (Figure 2(b))
and the area/performance quadratic polynomial A(q) (Figure 2(c))
are the outputs of the core model. The points along the Pareto fron-
tier are used as the search space for determining the best core con-
figuration by the multicore-scaling model. We discretized the fron-
tier into 100 points to consider 100 different core designs.
Voltage and frequency scaling: When deriving the Pareto fron-
tiers, each processor data point was assumed to operate at its opti-
mal voltage (Vdd
min
) and frequency setting (Freq
max
). Figure 2(d)
shows the result of voltage/frequency scaling on the design points
along the power/performance frontier. As depicted, at a fixed Vdd
setting, scaling down the frequency from Freq
max
, results in a pow-
er/performance point inside of the optimal Pareto curve, or a sub-
optimal design point. Scaling voltage up, on the other hand, and
operating at a new Vdd
min
and Freq
max
setting, results in a different
power-performance point along the frontier. Since we investigate
all the points along the Pareto frontier to find the optimal multi-
core configuration, voltage and frequency scaling does not require
special consideration in our study. If an application dissipates less
than the power budget, we assume that the voltage and frequency
scaling will be utilized to achieve the highest possible performance
with the minimum power increase. This is possible since voltage
and frequency scaling only changes the operating condition in a
Pareto-optimal fashion. Hence, we do not need to measure per-
benchmark power explicitly as reported in a recent study [12].
Table 3: CmpM
U
equations: corollaries of Amdahl’s Law for
power-constrained multicores.
Symmetric
N
S ym
(q) = min(
DIE
AREA
A(q)
,
T DP
P(q)
)
S peedup
S ym
( f, q) =
1
(1−f )
S
U
(q)
+
f
N
S ym
(q)S
U
(q)
Asymmetric
N
Asym
(q
L
, q
S
) = min(
DIE
AREA
−A(q
L
)
A(q
S
)
,
T DP−P(q
L
)
P(q
S
)
)
S peedup
Asym
( f, q
L
, q
S
) =
1
(1−f )
S
U
(q
L
)
+
f
N
Asym
(q
L
,q
S
)S
U
(q
S
)+S
U
(q
L
)
Dynamic
N
Dyn
(q
L
, q
S
) = min(
DIE
AREA
−A(q
L
)
A(q
S
)
,
T DP
P(q
S
)
)
S peedup
Dyn
( f, q
L
, q
S
) =
1
(1−f )
S
U
(q
L
)
+
f
N
Dyn
(q
L
,q
S
)S
U
(q
S
)
Composed
N
Composd
(q
L
, q
S
) = min(
DIE
AREA
(1+τ)A(q
S
)
,
T DP−Pq
L
P(q
S
)
)
S peedup
Composed
( f, q
L
, q
S
) =
1
(1−f )
S
U
(q
L
)
+
f
N
Com posed
(q
L
,q
S
)S
U
(q
S
)
4.3 Device Scaling × Core Scaling
To study core scaling in future technology nodes, we scaled the
45 nm Pareto frontiers to 8 nm by scaling the power and perfor-
mance of each processor data point using the projected DevM scal-
ing factors and then re-fitting the Pareto optimal curves at each
technology node. Performance, measured in SPECmark, is as-
sumed to scale linearly with frequency. This is an optimistic as-
sumption, which ignores the effects of memory latency and band-
width on the performance. Thus actual performance through scal-
ing is likely to be lower. Figures 2(e) and 2(f) show the scaled
Pareto frontiers for the ITRS and conservative scaling schemes.
Based on the optimistic ITRS roadmap predictions, scaling a mi-
croarchitecture (core) from 45 nm to 8 nm will result in a 3.9× per-
formance improvement and an 88% reduction in power consump-
tion. Conservative scaling, however, suggests that performance will
increase only by 34%, and power will decrease by 74%.
5. MULTICORE MODEL
We first present a simple upper-bound (CmpM
U
) model for mul-
ticore scaling that builds upon Amdahl’s Law to estimate the speedup
of area- and power-constrained multicores. To account for microar-
chitectural features and application behavior, we then develop a de-
tailed chip-level model (CmpM
R
) for CPU-like and GPU-like mul-
ticore organizations with different topologies. Both models use the
A(q) and P(q) frontiers from the core-scaling model.
5.1 Amdahl’s Law Upper-bounds: CmpM
U
Hill and Marty extended Amdahl’s Law [1] to study a range of
multicore topologies by considering the fraction of parallel code in
a workload [15]. Their models describe symmetric, asymmetric,
dynamic, and composed multicore topologies, considering area as
the constraint and using Pollack’s rule–the performance of a core
is proportional to the square root of its area–to estimate the perfor-
mance of multicores. We extend their work and incorporate power
as a primary design constraint, independent of area. Then, we de-
termine the optimal number of cores and speedup for topology. The
CmpM
U
model does not differentiate between CPU-like and GPU-
like architectures, since it abstracts away the chip organization.
Per Amdahl’s Law [1], system speedup is
1
(1−f )+
f
S
where f repre-
sents the portion that can be optimized, or enhanced, and S repre-
sents the speedup achievable on the enhanced portion. In the case
of parallel processing with perfect parallelization, f can be thought
of as the parallel portion of code and S as the number of proces-
sor cores. Table 3 lists the derived corollaries for each multicore
topology, where T DP is the chip power budget and DIE
AREA
is the
area budget. The q parameter denotes the performance of a single
core. Speedup is measured against a baseline core with perfor-
mance q
Baseline
. The upper-bound speedup of a single core over the
baseline is computed as S
U
(q) = q/q
Baseline
.
Symmetric Multicore: The parallel fraction ( f ) is distributed across
the N
S ym
(q) cores each of which has S
U
(q) speedup over the base-
line. The serial code-fraction, 1 − f , runs only on one core.
Asymmetric Multicore: All cores (including the large core), con-
tribute to execution of the parallel code. Terms q
L
and q
S
denote
performance of the large core and a single small core, respectively.
The number of small cores is bounded by the power consumption
or area of the large core.
Dynamic Multicore: Unlike the asymmetric case, if power is the
dominant constraint, the number of small cores is not bounded by
the power consumption of the large core. However, if area is the
dominant constraint, the number of small cores is bounded by the
area of the large core.
Composed Multicore: The area overhead supporting the com-
posed topology is τ. Thus, the area of small cores increases by
a factor of (1 + τ). No power overhead is assumed for the compos-
ability support in the small cores. We assume that τ increases from
10% up to 400% depending on the total area of the composed core.
We assume performance of the composed core cannot exceed per-
formance of a scaled single-core Nehalem at 45 nm. The composed
core consumes the power of a same-size uniprocessor core.
5.2 Realistic Performance Model: CmpM
R
The above corollaries provide a strict upper-bound on parallel
performance, but do not have the level of detail required to explore
microarchitectural features (cache organization, memory bandwidth,
number of threads per core, etc.) and workload behavior (mem-
ory access pattern and level of multithread parallelism in the ap-
plication). Guz et al. proposed a model to consider first-order im-
pacts of these additional microarchitectural features [13]. We ex-
tend their approach to build the multicore model that incorporates
application behavior, microarchitectural features, and physical con-
straints. Using this model, we consider single-threaded cores with
large caches to cover the CPU multicore design space and mas-
sively threaded cores with minimal caches to cover the GPU mul-
ticore design space. For each of these multicore organizations, we
consider the four possible topologies.
The CmpM
R
model formulates the performance of a multicore
in terms of chip organization (CPU-like or GPU-like), frequency,
CPI, cache hierarchy, and memory bandwidth. The model also in-
cludes application behaviors such as the degree of thread-level par-
allelism, the frequency of load and store instructions, and the cache
miss rate. To first order, the model considers stalls due to mem-
ory dependences and resource constraints (bandwidth or functional
units). The input parameters to the model, and how, if at all, they
are impacted by the multicore design choices are listed in Table 4.
Microarchitectural Features
Multithreaded performance (Per f ) of an Multithreaded performance
(Per f ) of an either CPU-like or GPU-like multicore running a fully
parallel ( f = 1) and multithreaded application is calculated in terms
of instructions per second in Equation (1) by multiplying the num-
ber of cores (N) by the core utilization (η) and scaling by the ratio
of the processor frequency to CPI
exe
:
Per f = min
N
f req
CPI
exe
η,
BW
max
r
m
× m
L1
× b
!
(1)