Decoupling Capacitors Placement at Board Level Adopting a Nature-Inspired Algorithm
TL;DR: The capacitance value and the location of three decoupling capacitors are optimized in order to obtain an input impedance below a specific mask, by using a nature-inspired algorithm, the genetic one, in combination with two electromagnetic solvers used to compute the objective function.
Abstract: Decoupling capacitors are fundamental keys for the reduction of transient noise in power delivery networks; their arrangement and values are crucial for reaching this goal. This work deals with the optimization of the decoupling capacitors of a power delivery network by using a nature-inspired algorithm. In particular, the capacitance value and the location of three decoupling capacitors are optimized in order to obtain an input impedance below a specific mask, by using a nature-inspired algorithm, the genetic one, in combination with two electromagnetic solvers used to compute the objective function. An experimental board is designed and manufactured; measurements are performed to validate the numerical results.
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01 Jul 2020
TL;DR: An optimization algorithm for accordingly placing decoupling capacitors one-by-one and iteratively evaluating the cost function of each PDN design solution is proposed, leading to a decap configuration that effectively takes into account the decap value, the parasitics inductance, and the decap location.
Abstract: The current demand in Power Distribution Network (PDN) design is characterized by the accurate placement of decoupling capacitors and the minimization of their number aimed at cost saving. The paper proposes an optimization algorithm for accordingly placing decoupling capacitors one-by-one and iteratively evaluating the cost function of each PDN design solution. This allows the designer to identify the minimum number of decaps whenever the input impedance satisfies the target impedance requirements. The algorithm is based on the Genetic Algorithm accordingly adapted for the specific application of PDN design. It may involve the evaluation of the input impedance at multiple locations, representing either multiple ICs, as well as multiple power input areas/pins of the same IC. The validation of the developed optimization algorithm is carried out by applying it to a manufactured PCB and by employing typical (low inductance) decaps for PDN design. The optimization process led to a decap configuration that effectively takes into account the decap value, the parasitics inductance, and the decap location. An accurate experimental test further validates the optimized PDN.
17 citations
TL;DR: An iterative optimization for decoupling capacitor placement on a power delivery network (PDN) is presented based on Genetic Algorithm and Artificial Neural Network to effectively provide results consistent with those obtained by a longer optimization based on commercial simulators.
Abstract: An iterative optimization for decoupling capacitor placement on a power delivery network (PDN) is presented based on Genetic Algorithm (GA) and Artificial Neural Network (ANN). The ANN is first trained by an appropriate set of results obtained by a commercial simulator. Once the ANN is ready, it is used within an iterative GA process to place a minimum number of decoupling capacitors for minimizing the differences between the input impedance at one or more location, and the required target impedance. The combined GA–ANN process is shown to effectively provide results consistent with those obtained by a longer optimization based on commercial simulators. With the new approach the accuracy of the results remains at the same level, but the computational time is reduced by at least 30 times. Two test cases have been considered for validating the proposed approach, with the second one also being compared by experimental measurements.
12 citations
TL;DR: In this paper, a genetic algorithm is used for the optimization of the decoupling capacitors in order to obtain the frequency spectrum of the input impedance in different positions on the network, below previously defined values.
Abstract: To reduce the noise created by a power delivery network, the number, the value of decoupling capacitors and their arrangement on the board are critical to reaching this goal. This work deals with specific improvements, implemented on a genetic algorithm, which used for the optimization of the decoupling capacitors in order to obtain the frequency spectrum of the input impedance in different positions on the network, below previously defined values. Measurements are performed on a specifically manufactured board in order to validate the effectiveness of the proposed algorithm and the optimization results obtained for a specific example board.
6 citations
Cites background or methods from "Decoupling Capacitors Placement at ..."
...Moreover, the low frequency portion can also be relaxed by ignoring the impact of the VRM impedance and taking into account the low frequency capacitive trend as the sum of the required total PDN capacitance [14]....
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...The presents work is carried out to solve several limitations in Reference [14] by achieving a more efficient and practical optimization process....
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...Although the GA developed in Reference [14] gave acceptable results, there were margins of improvements aiming to a more robust and stable algorithm capable of dealing with more complex PDN designs....
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...A preliminary work by the authors in Reference [14] where the GA has been adopted for finding the optimum number and values of decaps to be mounted on a PDN of a printed circuit board....
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...Although the GA developed in Reference [14] gave acceptable results, there were argins of i prove ents ai ing to a ore robust and stable algorith capable of dealing with ore co plex PDN designs....
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TL;DR: In this article , a multi-port constrained optimization methodology is presented for the optimal placement of decoupling capacitors in power distribution networks (PDNs) of printed circuit boards (PCBs).
Abstract: A multi-port constrained optimization methodology is presented for the optimal placement of decoupling capacitors in power distribution networks (PDNs) of printed circuit boards (PCBs). The proposed method is based on barrier methods and can simultaneously handle multiple ball grid array (BGA) devices and capacitor ports on practical power/ground plane pairs of polygonal shapes without restriction in the problem geometry. Semi-analytical expressions are developed for the magnitude of device port impedance that is set as the objective function. The placement optimization problem including constraints of planar boundaries and impedance specifications is cast into a matrix expression that meets Karush–Kuhn Tucker (KKT) conditions and solved through Newton–Raphson (N–R) iterations. The convergence of iterations is ensured by guaranteeing the positive definiteness of the system matrix through the Levenberg–Marquardt algorithm. Mutual coupling among multiple ports and discrete components of the problem domain is accounted for via matrix calculus techniques applied to the partial derivatives of optimization variables. The derivatives are evaluated accurately exploiting the semi-analytical relations developed for the distributed planar impedance. The proposed method is tested with several examples, and the results are observed to be in good agreement with those obtained from a numerical electromagnetic (EM) simulator while yielding significant speed-up.
2 citations
DOI•
12 Dec 2022
TL;DR: In this paper , the authors present a methodology to obtain the minimal number of decoupling capacitors for a 4-level hierarchical system to meet the on-chip voltage droop constraints and to optimize the location of those decoupled capacitors to meet a user-specified target impedance.
Abstract: It is increasingly challenging to satisfy the requirements placed on the power delivery network for a multilevel hierarchical system, due to aggressive voltage scaling and stringent limits on the chip-level voltage droop. This paper presents a methodology to obtain the minimal number of decoupling capacitors for a 4-level hierarchical system to meet the on-chip voltage droop constraints and to optimize the location of those decoupling capacitors to meet a user-specified target impedance. The number and location optimizations are performed using nature-based and Bayesian optimization algorithms along with the quantitative comparison of results.
References
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305 citations