Decoupling network optimization in high speed systems by mixed-integer programming
01 Jun 2014-pp 1010-1013
TL;DR: This paper provides a generic formulation for decoupling capacitor selection and placement problem which is solved by mixed-integer programming.
Abstract: Power Integrity is maintained in a high speed system by designing an efficient decoupling network This paper provides a generic formulation for decoupling capacitor selection and placement problem which is solved by mixed-integer programming A real-world example is presented for the same The minimum number of capacitors that could achieve the target impedance over the desired frequency range are found along with their optimal locations In order to solve an industrial problem, the s-parameters data of power plane geometry and capacitors are used for the accurate analysis including bulk capacitors and VRM
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Citations
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TL;DR: In this paper, an optimization algorithm using the Hessian minimization method, based on the Newton iteration, is proposed to evaluate the effectiveness of the placement of multiple decoupling capacitors on a power/ground plane pair.
Abstract: This article proposes an optimization algorithm using the Hessian minimization method, based on the Newton iteration, to evaluate the effectiveness of the placement of multiple decoupling capacitors on a power/ground plane pair. The exact effective decoupling regions are obtained using the Newton iteration method for each decoupling capacitor. The impedance of the IC port is lower than the target impedance no matter where the decoupling capacitor is placed in this region. To optimize specific capacitor placements in this region, the Newton iteration, based on the Hessian matrix, is used to determine the location where the impedance of the IC port is minimized at the antiresonant frequency of the plane pair. This placement optimization algorithm allows for a decoupling design method that can also be applied to a PDN with multiple decoupling capacitors for multiple IC ports. Compared with the method of random selection from within the effective decoupling area, the method proposed here requires fewer decoupling capacitors and less computational time.
26 Jul 2021
TL;DR: In this paper, a metaheuristic technique based generic framework for decoupling capacitor optimization in a practical power delivery network is presented, where the cumulative impedance of a power delivery system is minimized below the target impedance by optimal selection and placement of decoupled capacitors using state-of-the-art meta-heuristic algorithms.
Abstract: In VLSI circuits and systems, it is a common practice to reduce power supply noise in power delivery networks by decoupling capacitors. The optimal selection and placement of decoupling capacitors is crucial for maintaining power integrity efficiently. This paper presents a metaheuristic technique based generic framework for decoupling capacitor optimization in a practical power delivery network. The cumulative impedance of a power delivery network is minimized below the target impedance by optimal selection and placement of decoupling capacitors using state-of-the-art metaheuristic algorithms. A comparative analysis of the performance of these algorithms is presented with the insights of practical implementation.
References
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03 Oct 2005
TL;DR: In this article, the authors discuss strategies for locating and mounting decoupling capacitors in various situations as well as methods for estimating the total amount of decoupled capacitance required.
Abstract: Power bus decoupling is an important part of digital printed circuit board design. Effective strategies for implementing power bus decoupling depend on the board construction as well as the demands that the circuits place on the power distribution network. This paper discusses strategies for locating and mounting decoupling capacitors in various situations as well as methods for estimating the total amount of decoupling capacitance required
29 citations
TL;DR: In this paper, the optimal placement of decoupling capacitors in suppressing the input and transfer impedances of power-ground planes was investigated in high-speed digital printed circuit boards.
Abstract: In the high-speed digital printed circuit board, decoupling capacitors play an important role in lowering the power-ground planes impedance leading to the ground bounce noise in I/O ports while the logic is in transition. This paper investigates the optimal placement of decoupling capacitors in suppressing the input and transfer impedances of power-ground planes. The cavity model combines with genetic algorithm (GA) here to find the design specification and the optimal placement of the decoupling capacitors.
23 citations
17 Mar 2008
TL;DR: In this paper, the authors define the three important aspects of power integrity (PI), sufficiency, efficiency, and stability, and present how the power delivery system (PDS) can be designed, modeled, analyzed, and verified in a CAD environment.
Abstract: This paper defines the three important aspects of power integrity (PI), sufficiency, efficiency, and stability; and presents how the power delivery system (PDS) can be designed, modeled, analyzed, and verified in a CAD environment.
13 citations
20 May 2012
TL;DR: To maintain power integrity in a high speed system, an effective methodology for suppressing the cavity-mode anti-resonances' peaks is presented and optimal values and locations of decoupling capacitors are obtained.
Abstract: Swarm intelligence is applied to a module of high speed system design problem. To maintain power integrity in a high speed system, an effective methodology for suppressing the cavity-mode anti-resonances' peaks is presented. The optimal values and the optimal positions of the decoupling capacitors are found using three different swarm intelligence methods - particle swarm optimization, cuckoo search method and firefly algorithm. Optimum values and locations of decoupling capacitors are obtained, by which anti-resonances' peaks of loaded board are minimized.
10 citations
"Decoupling network optimization in ..." refers background in this paper
...The selection of decoupling capacitors and their positions on the board affect the system performance [3]-[5]....
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19 Mar 2012
TL;DR: To maintain Power Integrity in a high speed system, an effective methodology for suppressing the cavity-mode anti-resonances peaks is presented and optimum values and the optimal positions of the decoupling capacitors are found using Particle Swarm Optimization.
Abstract: To maintain Power Integrity in a high speed system, an effective methodology for suppressing the cavity-mode anti-resonances peaks is presented. The optimum values and the optimal positions of the decoupling capacitors are found using Particle Swarm Optimization, which leads to optimum impedance of power plane loaded with decoupling capacitors. Optimum number of capacitors and their values, by which impedance of loaded board is matched below the target impedance of the system, are found.
8 citations
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