Defect Detection and Defect-Tolerant Design of a Multi-port SRAM

TLDR: In this paper, a register file with a structure of three-port SRAM cell and a differential current-mode sense amplifier for read circuitry is presented, and a read disturb fault for multi-port memories is tested on the faulty cell by simultaneous read operations with different numbers of ports.

Abstract: Static random memory (SRAM)-based multi-port memory cell can perform multiple read and write operations simultaneously, thus increasing data throughput. With the continuous scaling of transistor feature size, designing low-power robust memories for microprocessors and investigating their failure characteristics become critical. In this work, we present a register file with a structure of three-port SRAM cell and a differential current-mode sense amplifier for read circuitry. We then study the fault models for resistive defect within the SRAM cell and its failure boundary. The presence of resistive-open defects has become more and more important, due to ever-increasing complexity. A read disturb fault for multi-port memories is tested on the faulty cell by simultaneous read operations with different numbers of ports. Resistive-open defects in embedded-SRAM core cells were identified, and a March test was proposed to cover the fault models. The proposed circuit is simulated and validated for 100 runs using Monte Carlo simulations.