# Degradation of Alias Rejection in Continuous-Time Bandpass Delta-Sigma Converters due to Weak Loop Filter Nonlinearities

26 May 2019-pp 1-5

TL;DR: The expression for alias rejection is derived when the OTA used in the first integrator is realized as a two stage feed-forward compensated structure and simulation results confirm the theory.

Abstract: We show that the nonlinearity of the first integrator's operational transconductance amplifier (OTA) significantly degrades the alias rejection of a bandpass CTΔEM in the presence of OTA parasitics. We derive the expression for alias rejection when the OTA used in the first integrator is realized as a two stage feed-forward compensated structure. Simulation results confirm the theory.

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08 Nov 2004

TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.

Abstract: Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.

2,093 citations

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TL;DR: In this paper, a software-defined radio receiver is designed from a low-power ADC perspective, exploiting programmability of windowed integration sampler and clock-programmable discrete-time analog filters.

Abstract: A software-defined radio receiver is designed from a low-power ADC perspective, exploiting programmability of windowed integration sampler and clock-programmable discrete-time analog filters. To cover the major frequency bands in use today, a wideband RF front-end, including the low-noise amplifier (LNA) and a wide tuning-range synthesizer, spanning over 800 MHz to 6 GHz is designed. The wideband LNA provides 18-20 dB of maximum gain and 3-3.5 dB of noise figure over 800 MHz to 6 GHz. A low 1/f noise and high-linearity mixer is designed which utilizes the passive mixer core properties and provides around +70 dBm IIP2 over the bandwidth of operation. The entire receiver circuits are implemented in 90-nm CMOS technology. Programmability of the receiver is tested for GSM and 802.11g standards

420 citations

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01 Aug 1974

TL;DR: Analytical modeling of communication receivers to account for their nonlinear response to multiple input signals is discussed, based on the application of the Wiener-Volterra analysis of nonlinear functionals.

Abstract: Analytical modeling of communication receivers to account for their nonlinear response to multiple input signals is discussed. The method is based on the application of the Wiener-Volterra analysis of nonlinear functionals. The derived analytical relations were embodied in a computer program which provides nonlinear transfer functions of large circuits specified by their parameters. This method was applied to the prediction of behavior of communication receivers in the presence of interference. Examples illustrate the method and demonstrate its validity in the small-signal region.

418 citations

### "Degradation of Alias Rejection in C..." refers methods in this paper

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TL;DR: A CMOS IF receiver that performs amplification, mixing and bandpass A/D conversion is presented and the receiver is described.

Abstract: An 81-MHz CMOS IF receiver for digital wireless applications is presented. The receiver consists of a continuous-time IF amplifier, a subsampling switched-capacitor gain stage, and a sixth-order bandpass /spl Sigma//spl Delta/ A/D converter. Incorporating 24 dB of programmable gain, the receiver achieves 92 dB of dynamic range in a 200 kHz bandwidth. Due to its IF sampling nature, the reciever is immune to de offset, flicker noise, and errors due to mismatches between I and Q signal paths. By utilizing a pseudo two-path resonator architecture in the bandpass /spl Sigma//spl Delta/ A/D converter, a stable passband center frequency which is immune to capacitor mismatch is achieved. Implemented in 0.8-/spl mu/m CMOS, this chip uses a single 3 V supply and consumes 14.4 mW of power.

135 citations

### "Degradation of Alias Rejection in C..." refers methods in this paper

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09 Feb 2011

TL;DR: Robust Sigma Delta Converters presents a requirement derivation of a Sigma Delta modulator applied in a receiver for cellular and connectivity, and shows trade-offs between RF and ADC.

Abstract: Sigma Delta converters are a very popular choice for the A/D converter in multi-standard, mobile and cellular receivers. Key A/D converter specifications are high dynamic range, robustness, scalability, low-power and low EMI. Robust Sigma Delta Converters presents a requirement derivation of a Sigma Delta modulator applied in a receiver for cellular and connectivity, and shows trade-offs between RF and ADC. The book proposes to categorize these requirements in 5 quality indicators which can be used to qualify a system, namely accuracy, robustness, flexibility, efficiency and emission. In the book these quality indicators are used to categorize Sigma Delta converter theory. A few highlights on each of these quality indicators are; Quality indicators: provide a means to quantify system quality.Accuracy: introduction of new Sigma Delta Modulator architectures.Robustness: a significant extension on clock jitter theory based on phase and error amplitude error models. Extension of the theory describing aliasing in Sigma Delta converters for different types of DACs in the feedback loop. Flexibility: introduction of a Sigma Delta converter bandwidth scaling theory leading to very flexible Sigma Delta converters. Efficiency: introduction of new Figure-of-Merits which better reflect performance-power trade-offs. Emission: analysis of Sigma Delta modulators on emission is not part of the bookThe quality indicators also reveal that, to exploit nowadays advanced IC technologies, things should be done as much as possible digital up to a limit where system optimization allows reducing system margins. At the end of the book Sigma Delta converter implementations are shown which are digitized on application-, architecture-, circuit- and layout-level.Robust Sigma Delta Converters is written under the assumption that the reader has some background in receivers and in A/D conversion.

20 citations

### "Degradation of Alias Rejection in C..." refers background in this paper

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