DELIGHT.SPICE: an optimization-based system for the design of integrated circuits
01 Apr 1988-IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE)-Vol. 7, Iss: 4, pp 501-519
TL;DR: The DELIGHT.SPICE tool, a union of the DELIGHT interactive optimization-based computer-aided-design system and the SPICE circuit analysis program, is presented, yielding substantial improvement in circuit performance.
Abstract: DELIGHT.SPICE is the union of the DELIGHT interactive optimization-based computer-aided-design system and the SPICE circuit analysis program. With the DELIGHT.SPICE tool, circuit designers can take advantage of recent powerful optimization algorithms and a methodology that emphasizes designer intuition and man-machine interaction. Designer and computer are complementary in adjusting parameters of electronic circuits automatically to improve their performance criteria and to study complex tradeoffs between multiple competing objectives, while simultaneously satisfying multiple-constraint specifications. The optimization runs much more efficiently than previously because the SPICE program used has been enhanced to perform DC, AC, and transient sensitivity computation. Industrial analog and digital circuits have been redesigned using this tool, yielding substantial improvement in circuit performance. >
Citations
More filters
01 Dec 2000
TL;DR: This survey presents an overview of recent advances in the state of the art for computer-aided design (CAD) tools for analog and mixed-signal integrated circuits (ICs) and outlines progress on the various design problems involved.
Abstract: This survey presents an overview of recent advances in the state of the art for computer-aided design (CAD) tools for analog and mixed-signal integrated circuits (ICs). Analog blocks typically constitute only a small fraction of the components on mixed-signal ICs and emerging systems-on-a-chip (SoC) designs. But due to the increasing levels of integration available in silicon technology and the growing requirement for digital systems to communicate with the continuous-valued external world, there is a growing need for CAD tools that increase the design productivity and improve the quality of analog integrated circuits. This paper describes the motivation and evolution of these tools and outlines progress on the various design problems involved: simulation and modeling, symbolic analysis, synthesis and optimization, layout generation, yield analysis and design centering, and test. This paper summarizes the problems for which viable solutions are emerging and those which are still unsolved.
579 citations
Cites background from "DELIGHT.SPICE: an optimization-base..."
...For a limited set of parameters circuit optimization was already possible in DELIGHT.SPICE [ 89 ]....
[...]
TL;DR: A new method for determining component values and transistor dimensions for CMOS operational amplifiers (op-amps) is described, showing in detail how the method can be used to size robust designs, i.e., designs guaranteed to meet the specifications for a variety of process conditions and parameters.
Abstract: We describe a new method for determining component values and transistor dimensions for CMOS operational amplifiers (op-amps). We observe that a wide variety of design objectives and constraints have a special form, i.e., they are posynomial functions of the design variables. As a result, the amplifier design problem can be expressed as a special form of optimization problem called geometric programming, for which very efficient global optimization methods have been developed. As a consequence we can efficiently determine globally optimal amplifier designs or globally optimal tradeoffs among competing performance measures such as power, open-loop gain, and bandwidth. Our method, therefore, yields completely automated sizing of (globally) optimal CMOS amplifiers, directly from specifications. In this paper, we apply this method to a specific widely used operational amplifier architecture, showing in detail how to formulate the design problem as a geometric program. We compute globally optimal tradeoff curves relating performance measures such as power dissipation, unity-gain bandwidth, and open-loop gain. We show how the method can he used to size robust designs, i.e., designs guaranteed to meet the specifications for a variety of process conditions and parameters.
540 citations
Cites background or methods from "DELIGHT.SPICE: an optimization-base..."
...The robust design problem can be formulated as a so-called semi-infinite programming problem, in which the constraints must hold for all values of some parameter that ranges over an interval, as in [75], which used DELIGHT....
[...]
...We also verify some of our designs using high fidelity SPICE models, and briefly discuss how our method can be extended to handle short-channel effects....
[...]
...A longer version of this paper, which includes more detail about the models, some of the derivations, and SPICE simulation parameters, is available at the authors’ web site [51]....
[...]
...The classical methods can be used with more complicated circuit models, including even full SPICE simulations in each iteration, as in DELIGHT....
[...]
...SPICE [75] (which uses the general-purpose optimizer DELIGHT [76]) and ECSTASY [86]....
[...]
TL;DR: A hierarchically structured framework for analog circuit synthesis is described and mechanisms are described that select from among alternate design styles and translate performance specifications from one level in the hierarchy to the next lower, more concrete level.
Abstract: A hierarchically structured framework for analog circuit synthesis is described. This hierarchical structure has two important features: it decomposes the design task into a sequence of smaller tasks with uniform structure, and it simplifies the reuse of design knowledge. Mechanisms are described that select from among alternate design styles and translate performance specifications from one level in the hierarchy to the next lower, more concrete level. A prototype implementation, OASYS, synthesizes sized transistor schematics for CMOS operational amplifiers from performance specifications and process parameters. Measurements from detailed circuit simulation and from actual fabricated analog ICs based on OASYS-synthesized designs demonstrate that OASYS is capable of synthesizing functional circuits. >
417 citations
TL;DR: A new synthesis strategy that can automate fully the path from an analog circuit topology and performance specifications to a sized circuit schematic and relies on asymptotic waveform evaluation to predict circuit performance and simulated annealing to solve a novel unconstrained optimization formulation of the circuit synthesis problem is presented.
Abstract: We present a new synthesis strategy that can automate fully the path from an analog circuit topology and performance specifications to a sized circuit schematic. This strategy relies on asymptotic waveform evaluation to predict circuit performance and simulated annealing to solve a novel unconstrained optimization formulation of the circuit synthesis problem. We have implemented this strategy in a pair of tools called ASTRX and OBLX. To show the generality of our new approach, we have used this system to resynthesize essentially all the analog synthesis benchmarks published in the past decade; ASTRX/OBLX has resynthesized circuits in an afternoon that, for some prior approaches, had required months. To show the viability of the approach on difficult circuits, we have resynthesized a recently published (and patented), high-performance operational amplifier; ASTRX/OBLX achieved performance comparable to the expert manual design. And finally, to test the limits of the approach on industrial-sized problems, we have synthesized the component cells of a pipelined A/D converter; ASTRX/OBLX successfully generated cells 2-3/spl times/ more complex than those published previously.
347 citations
07 Nov 1988
TL;DR: The results show that binary decision diagrams (BDD) with the proposed ordering method can verify almost all benchmark circuits in less than several central processor unit (CPU) minutes, which is one hundred times faster than times reported in the literature.
Abstract: R.E. Bryant proposed a method to handle logic expressions (IEEE Trans. Comp., vol.25, no.8, p.667-91, 1986) which is based on binary decision diagrams (BDD) with restriction; variable ordering ix fixed throughout a diagram. The method is more efficient than other methods proposed so far and depends heavily on variable ordering. A simple but powerful algorithm for variable ordering is developed. The algorithm tries to find a variable ordering which minimizes the number of crosspoints of nets when the circuit diagram is drawn. This is applied to the Boolean comparison of ISCAS benchmark circuits for test pattern generation. The results show that binary decision diagrams (BDD) with the proposed ordering method can verify almost all benchmark circuits in less than several central processor unit (CPU) minutes, which is one hundred times (or more) faster than times reported in the literature. Some techniques for circuit evaluation ordering are also mentioned. >
278 citations
References
More filters
IBM1
TL;DR: In this article, a modified nodal analysis (MNA) method is proposed, which retains the simplicity and other advantages of nodal Analysis while removing its limitations, and a simple and effective pivoting scheme is also given.
Abstract: The nodal method has been widely used for formulating circuit equations in computer-aided network analysis and design programs. However, several limitations exist in this method including the inability to process voltage sources and current-dependent circuit elements in a simple and efficient manner. A modified nodal analysis (MNA) method is proposed here which retains the simplicity and other advantages of nodal analysis while removing its limitations. A simple and effective pivoting scheme is also given. Numerical examples are used to compare the MNA method with the tableau method. Favorable results are observed for the MNA method in terms of the dimension, number of nonzeros, and fill-ins for comparable circuit matrices.
1,337 citations
01 Jan 2003
TL;DR: A new transistor sizing algorithm, which couples synchronous timing analysis with convex optimization techniques, is presented, which shows that any point found to be locally optimal is certain to be globally optimal.
Abstract: A new transistor sizing algorithm, which couples synchronous timing analysis with convex optimization techniques, is presented. Let A be the sum of transistor sizes, T the longest delay through the circuit, and K a positive constant. Using a distributed RC model, each of the following three programs is shown to be convex: 1) Minimize A subject to T < K. 2) Minimize T subject to A < K. 3) Minimize AT K . The convex equations describing T are a particular class of functions called posynomials. Convex programs have many pleasant properties, and chief among these is the fact that any point found to be locally optimal is certain to be globally optimal TILOS (Timed Logic Synthesizer) is a program that sizes transistors in CMOS circuits. Preliminary results of TILOS’s transistor sizing algorithm are presented.
542 citations
TL;DR: In this paper, the authors derived a related adjoint network representation and sensitivity coefficients for networks containing a very broad class of elements: those that admit a parametric representation, and a brief discussion is given as to how these results may be exploited in a general automated network design scheme.
Abstract: It has been established that the adjoint network and network sensitivities play important roles in automated network design algorithms. The present paper derives a related adjoint network representation and sensitivity coefficients for networks containing a very broad class of elements: those that admit a parametric representation. A brief discussion is given as to how these results may be exploited in a general automated network design scheme.
503 citations
TL;DR: The main analytical tool in this paper is an extension to infinite-dimensional spaces of the “generalized gradient” previously introduced by the author, and the calculus of the generalized gradient is explored as a preliminary step.
Abstract: We consider a mathematical programming problem on a Banach space, and we derive necessary conditions for optimality in Lagrange multiplier form. We prove further that “most mathematical programming problems are normal.” The novelty of our approach lies on the one hand in the absence of both differentiability and convexity hypotheses on the functions delimiting the problem, and on the other hand in the method of proof, which is new. The approach unifies the well-known smooth and convex cases besides treating a new general class of problems.
The main analytical tool in this paper is an extension to infinite-dimensional spaces of the “generalized gradient” previously introduced by the author. The calculus of the generalized gradient is explored as a preliminary step.
463 citations
IBM1
TL;DR: This work surveys contemporary optimization techniques and relates these to optimization problems which arise in the design of integrated circuits, and focuses on those multiobjective constrained optimization techniques which are appropriate to this environment.
Abstract: We survey contemporary optimization techniques and relate these to optimization problems which arise in the design of integrated circuits. Theory, algorithms and programs are reviewed, and an assessment is made of the impact optimization has had and will have on integrated-circuit design. Integrated circuits are characterized by complex tradeoffs between multiple nonlinear objectives with multiple nonlinear and sometimes nonconvex constraints. Function and gradient evaluations require the solution of very large sets of nonlinear differential equations, consequently they are inaccurate and extremely expensive. Furthermore, the partmeters to be optimized are subject to inherent statistical fluctuations. We focus on those multiobjective constrained optimization techniques which are appropriate to this environment.
261 citations