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BookDOI

Delta-sigma data converters

02 Jan 1994-pp 317-339
About: This article is published in Telecommunications and Signal Processing.The article was published on 1994-01-02. It has received 1028 citations till now. The article focuses on the topics: Delta-sigma modulation.
Citations
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Proceedings ArticleDOI
10 Dec 2002
TL;DR: In this paper, it is shown that Lebesgue sampling gives better performance for some simple systems than traditional Riemann sampling, which is an analog of integration theory and is called event-based sampling.
Abstract: The normal approach to digital control is to sample periodically in time. Using an analog of integration theory we can call this Riemann sampling. Lebesgue sampling or event based sampling is an alternative to Riemann sampling. It means that signals are sampled only when measurements pass certain limits. In this paper it is shown that Lebesgue sampling gives better performance for some simple systems.

961 citations

Journal ArticleDOI
TL;DR: This paper investigates some simple first order systems with event based sampling and compares achieved closed loop variance and sampling rate with results from periodic sampling and shows that event based sampled gives better performance than periodic sampling.

684 citations

Journal ArticleDOI
TL;DR: This paper presents a complete set of blocks implemented in the popular MATLAB SIMULINK environment, which allows designers to perform time-domain behavioral simulations of switched-capacitor sigma-delta (/spl Sigma//spl Delta/) modulators.
Abstract: This paper presents a complete set of blocks implemented in the popular MATLAB SIMULINK environment, which allows designers to perform time-domain behavioral simulations of switched-capacitor (SC) sigma-delta (/spl Sigma//spl Delta/) modulators. The proposed set of blocks takes into account most of the SC /spl Sigma//spl Delta/ modulator nonidealities, such as sampling jitter, kT/C noise, and operational amplifier parameters (white noise, finite DC gain, finite bandwidth, slew rate and saturation voltages). For each block, a description of the considered effect as well as all of the implementative details are provided. The proposed simulation environment is validated by comparing the simulated behavior with the experimental results obtained from two actual circuits, namely a second-order low-pass and a sixth-order bandpass SC /spl Sigma//spl Delta/ modulator.

413 citations


Cites background from "Delta-sigma data converters"

  • ...…ratio (SNR) or signal-to-noise and distortion ratio (SNDR).1 In principle, various approaches for transient simulation which include device models (such as SPICE), finite-difference equations (such as SWITCAP), custom numerical models (typically in C language), etc., are already available....

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Book ChapterDOI
01 Jan 2008
TL;DR: The architecture of a general structure for event based control is presented, the key elements are an event detector, an observer, and a control signal generator, which can be regarded as a generalized data-hold.
Abstract: Summary. In spite of the success of traditional sampled-data theory in computer control it has some disadvantages particularly for distributed, asynchronous, and multi-rate system. Event based sampling is an alternative which is explored in this paper. A simple example illustrates the differences between periodic and event based sampling. The architecture of a general structure for event based control is presented. The key elements are an event detector, an observer, and a control signal generator, which can be regarded as a generalized data-hold. Relations to nonlinear systems are discussed. Design of an event based controller is illustrated for a simple model of a micro-mechanical accelerometer.

393 citations

Journal ArticleDOI
TL;DR: A wide bandwidth continuous-time sigma-delta ADC, operating between 20 and 40 MS/s output data rate, is implemented in 130-nm CMOS and the degradation of modulator stability due to excess loop delay is avoided with a new architecture.
Abstract: A wide bandwidth continuous-time sigma-delta ADC, operating between 20 and 40 MS/s output data rate, is implemented in 130-nm CMOS. The circuit is targeted for applications that demand high bandwidth, high resolution, and low power, such as wireless and wireline communications, medical imaging, video, and instrumentation. The third-order continuous-time SigmaDelta modulator comprises a third-order RC operational-amplifier-based loop filter and 4-bit internal quantizer operating at 640 MHz. A 400-fs rms jitter LC PLL with 450-kHz bandwidth is integrated, generating the low-jitter clock for the jitter-sensitive continuous-time SigmaDelta ADC from a single-ended input clock between 13.5 and 40 MHz. To reduce clock jitter sensitivity, nonreturn-to-zero (NRZ) DAC pulse shaping is used. The excess loop delay is set to half the sampling period of the quantizer and the degradation of modulator stability due to excess loop delay is avoided with a new architecture. The SigmaDelta ADC achieves 76-dB SNR, -78-dB THD, and a 74-dB SNDR or 12 ENOB over a 20-MHz signal band at an OSR of 16. The power consumption of the CT SigmaDelta modulator itself is 20 mW and in total the ADC dissipates 58 mW from the 1.2-V supply

314 citations