Design and analysis for a miniature CMOS SPDT switch using body-floating technique to improve power performance
10 Jan 2006-IEEE Transactions on Microwave Theory and Techniques (Institute of Electrical and Electronics Engineers Inc.)-Vol. 54, Iss: 1, pp 31-39
TL;DR: In this paper, a low insertion-loss single-pole double-throw switch in a standard 0.18/spl mu/m complementary metal-oxide semiconductor (CMOS) process was developed for 2.4 and 5.8 GHz wireless local area network applications.
Abstract: A low insertion-loss single-pole double-throw switch in a standard 0.18-/spl mu/m complementary metal-oxide semiconductor (CMOS) process was developed for 2.4- and 5.8-GHz wireless local area network applications. In order to increase the P/sub 1dB/, the body-floating circuit topology is implemented. A nonlinear CMOS model to predict the switch power performance is also developed. The series-shunt switch achieves a measured P/sub 1dB/ of 21.3 dBm, an insertion loss of 0.7 dB, and an isolation of 35 dB at 2.4 GHz, while at 5.8 GHz, the switch attains a measured P/sub 1dB/ of 20 dBm, an insertion loss of 1.1 dB, and an isolation of 27 dB. The effective chip size is only 0.03 mm/sup 2/. The measured data agree with the simulation results well, including the power-handling capability. To our knowledge, this study presents low insertion loss, high isolation, and good power performance with the smallest chip size among the previously reported 2.4- and 5.8-GHz CMOS switches.
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TL;DR: In this paper, the authors describe the design and measurement of a wideband (W-band) passive radiometer chip developed in a standard 0.12-?m SiGe BiCMOS technology (IBM8HP, ft /fmax = 200/265 GHz).
Abstract: This paper describes the design and measurement of a wideband (W-band) passive radiometer chip developed in a standard 0.12-?m SiGe BiCMOS technology (IBM8HP, ft /fmax = 200/265 GHz). Design equations, simulations, and measurements are presented for a 94-GHz square-law detector and wideband low noise amplifier, and an 80-110-GHz single-pole double-throw switch. A total-power radiometer is presented, which can achieve a temperature resolution of ? 0.69 K (30-ms integration time) with periodic calibration or chopping above 10 kHz. A switched Dicke radiometer chip is also presented, which addresses the 1/f noise of the total-power radiometer, and can achieve a temperature resolution of 0.83 K with a 30-ms integration time. This performance is comparable to current III-V imaging modules, and demonstrates, to our knowledge, the first implementation of a SiGe or CMOS W -band radiometer on a single chip.
180 citations
TL;DR: The analysis shows that a series-only architecture using the customized transistor layout achieves better insertion loss and reasonable isolation, and a double-well body-floating technique is proposed and its effects are discussed.
Abstract: This paper presents the comprehensive considerations of CMOS transmit/receive (T/R) switch design towards ultra-wideband and over 15-GHz frequencies. Techniques for minimizing parasitics and increasing linearity are discussed. A customized transistor layout is proposed for T/R switch design and its effects on insertion loss and isolation are studied. The analysis shows that a series-only architecture using the customized transistor layout achieves better insertion loss and reasonable isolation. A double-well body-floating technique is proposed and its effects are discussed. A differential switch architecture without shunt arms is designed and verified by experimental results. Fabricated in 0.13-mum triple-well CMOS, the T/R switch exhibits less than 2 dB insertion loss and higher than 21 dB isolation up to 20 GHz. With resistive body floating and differential architecture, the high linearity is of ultra-wideband characteristic, more than 30-dBm power 1-dB compression point (P1dB) is obtained up to 20 GHz in only 0.03 mm2 active die area.
138 citations
Cites background or methods from "Design and analysis for a miniature..."
...8 GHz and reported in [6], the result shows that 20–21 dBm can be obtained by floating the P-well through resistors....
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...At the same time, the presence of shunt arm degrades the power handling capability as the unintentional turn on of the shunt transistor increases loss significantly [5], [6]....
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...ized by using a large resistor to bias the bulk [6]....
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...Another view of linearity problem is from the DC I-V characteristics [6]....
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...Conventionally, the T/R switch design follows a series/shunt architecture [2]–[4], [6], [8], [11], as shown in Fig....
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TL;DR: In this paper, a fully integrated ultra-broadband transmit/receive (T/R) switch was developed using nMOS transistors with a deep n-well in a standard 0.18mum CMOS process, and demonstrates unprecedented insertion loss, isolation, power handling, and linearity.
Abstract: A fully integrated ultra-broadband transmit/receive (T/R) switch has been developed using nMOS transistors with a deep n-well in a standard 0.18-mum CMOS process, and demonstrates unprecedented insertion loss, isolation, power handling, and linearity. The new CMOS T/R switch exploits patterned-ground-shield on-chip inductors together with MOSFET's parasitic capacitances to synthesize artificial transmission lines, which result in low insertion loss over an extremely wide bandwidth. Negative bias to the bulk or positive bias to the drain of the MOSFET devices with floating bulk is used to reduce effects of the parasitic diodes, leading to enhanced linearity and power handling for the switch. Within dc-10, 10-18, and 18-20 GHz, the developed CMOS T/R switch exhibits insertion loss of less than 0.7, 1.0, and 2.5 dB and isolation between 32-60, 25-32, and 25-27 dB, respectively. The measured 1-dB power compression point and input third-order intercept point reach as high as 26.2 and 41 dBm, respectively. The new CMOS T/R switch has a die area of only 230 mumtimes250 mum. The achieved ultra-broadband performance and high power-handling capability, approaching those achieved in GaAs-based T/R switches, along with the full-integration ability confirm the usefulness of switches in CMOS technology, and demonstrate their great potential for many broadband CMOS radar and communication applications
130 citations
Cites background from "Design and analysis for a miniature..."
...…Identifier 10.1109/TMTT.2006.888944 Owing to low mobility, high substrate conductivity, low breakthrough voltage, and various parasitic parameters of CMOS processes, it is very challenging to design CMOS switches to achieve low-insertion loss, high isolation, wide bandwidth, and high power…...
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...This T/R switch, however, exhibits insertion loss not as good as its GaAs counterparts due to the high loss of CPW realized on the conductive silicon substrate and the loss associated with the MOSFETs....
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TL;DR: A fully integrated single-pole-double-throw transmit/receive switch has been designed and fabricated in standard bulk 90-nm complementary metaloxide semiconductor (CMOS) technology.
Abstract: A fully integrated single-pole-double-throw transmit/receive switch has been designed and fabricated in standard bulk 90-nm complementary metal-oxide semiconductor (CMOS) technology. Traveling wave concept was used to minimize the insertion loss at higher frequency and widen the operating bandwidth. The switch exhibits a measured insertion loss of 2.7 -dB, an input 1-dB compression point (input P1 dB) of 15 dBm, and a 29-dB isolation at the center frequency of 77 GHz. The total chip size is only 0.57 times 0.42 mm 2 including all testing pads. To our knowledge, this is the first CMOS switch demonstrated beyond 50 GHz, and the performances rival those monolithic microwave integrated circuit switches using standard GaAs PHEMTs
101 citations
Cites methods from "Design and analysis for a miniature..."
...It is also noted that in order to increase the power handling capacity, the floating-body technique is utilized in this design, similar to that in [6]....
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...A simple method using body-floating technique to increase the power handling capacity of a CMOS switch without increasing additional area is proposed in [6]....
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03 Apr 2012
TL;DR: This paper presents a fully integrated CMOS 60-GHz transceiver chipset for short-range and high-speed wireless communication, composed of two chips, an RF chip with in-package antenna, and a baseband chip including PHY and MAC layer.
Abstract: This paper presents a fully integrated CMOS 60-GHz transceiver chipset for short-range and high-speed wireless communication. The target application of the short-range communication is less than 5-cm communication distance and more than 2-Gb/s throughput for file transfer. In order to achieve file transfer, physical (PHY) layers with error packet correction and media access control (MAC) layer with frame-exchanging function are implemented. The MAC is designed to have a high-efficiency feature due to short interval DATA/Acknowledgement (ACK) frame exchange. It is realized by fast transmitter (TX)/receiver (RX) switching. A bonding wire-based in-package antenna is adopted using a standard BGA package without any off-chip 60-GHz components. The proposed chipset is composed of two chips, an RF chip with in-package antenna, and a baseband chip including PHY and MAC layer. The fabricated chipset achieves 2.62-Gb/s PHY data rate, 2.07-Gb/s MAC throughput, and energy consumption of 651 pJ/bit in 3-cm distance.
101 citations
Additional excerpts
...Conventional on-chip switch circuit in CMOS uses serial and parallel NMOS switches [9] that make large loss in the 60-GHz band or...
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References
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TL;DR: In this article, a large-signal model for HEMTs and MESFETs, capable of modeling the currentvoltage characteristic and its derivatives, including the characteristic transconductance peak, gate-source and gate-drain capacitances, is proposed.
Abstract: A large-signal model for HEMTs and MESFETs, capable of modeling the current-voltage characteristic and its derivatives, including the characteristic transconductance peak, gate-source and gate-drain capacitances, is proposed. Model parameter extraction is straightforward and is demonstrated for different submicron gate-length HEMT devices including different delta -doped pseudomorphic HEMTs on GaAs and lattice matched to InP, and a commercially available MESFET. Measured and modeled DC and S-parameters are compared and found to coincide well. >
519 citations
TL;DR: In this article, a single-pole double-throw transmit/receive switch for 30-V applications has been fabricated in a 05/spl mu/m CMOS process, which exhibits a 07-dB insertion loss, a 17-dBm power 1-dB compression point (P/sub 1 dB/), and a 42-dB isolation at 928 MHz.
Abstract: A single-pole double-throw transmit/receive switch for 30-V applications has been fabricated in a 05-/spl mu/m CMOS process An analysis shows that substrate resistances and source/drain-to-body capacitances must be lowered to decrease insertion loss The switch exhibits a 07-dB insertion loss, a 17-dBm power 1-dB compression point (P/sub 1 dB/), and a 42-dB isolation at 928 MHz The low insertion loss is achieved by optimizing the transistor widths and bias voltages, by minimizing the substrate resistances, and by dc biasing the transmit and receive nodes, which decreases the capacitances while increasing the power 1-dB compression point The switch has adequate insertion loss, isolation, P/sub 1 dB/, and IP/sub 3/ for a number of 900-MHz ISM band applications requiring a moderate peak transmitter power level (/spl sim/15 dBm)
176 citations
TL;DR: Results show that the switch design is suitable for narrow-band applications requiring a moderate-high transmitter power level (<1 W), and the linearity obtained in the transmit mode is the highest reported to date in a standard CMOS process.
Abstract: CMOS transmit-receive (T/R) switches have been integrated in a 0.18-/spl mu/m standard CMOS technology for wireless applications at 2.4 and 5.2 GHz. This switch design achieves low loss and high linearity by increasing the substrate impedance of a MOSFET at the frequency of operation using a properly tuned LC tank. The switch design is asymmetric to accommodate the different linearity and isolation requirements in the transmit and receive modes. In the transmit mode, the switch exhibits 1.5-dB insertion loss, 28-dBm power, 1-dB compression point (P/sub 1dB/), and 30-dB isolation, at 2.4 and 5.2 GHz. In the receive mode, the switch achieves 1.6-dB insertion loss, 11.5-dBm P/sub 1dB/, and 15-dB isolation, at 2.4 and 5.2 GHz. The linearity obtained in the transmit mode is the highest reported to date in a standard CMOS process. The switch passes the 4-kV Human Body Model electrostatic discharge test. These results show that the switch design is suitable for narrow-band applications requiring a moderate-high transmitter power level (<1 W).
157 citations
"Design and analysis for a miniature..." refers background or methods in this paper
...When the input power is 19 dBm, the dynamic load line of the 180- m series on-state transistor is still within the linear region of the dc–IV curve [see Fig....
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...Switches using high and low substrate resistances in a 0.18- m CMOS process have demonstrated good insertion loss [5], but required a large area of substrate contact to implement a low substrate resistance switch....
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09 Jun 1998
TL;DR: This paper describes a unified device model realized with a lumped resistance network suitable for simulations of both RF and baseband analog circuits and verifies the accuracy of the model to measured data on both device and circuit levels.
Abstract: With the advent of submicron technologies, GHz RF circuits can now be realized in a standard CMOS process. A major barrier to the realization of robust commercial CMOS RF components is the lack of adequate models which accurately predict MOSFET device behavior at high frequencies. The conventional microwave table-lookup-based approach requires a large database obtained from numerous device measurements and computationally intense simulations for accurate results. This method becomes prohibitively complex when used to simulate highly integrated CMOS communication systems; hence, a compact model, valid for a broad range of bias conditions and operating frequencies is desirable. BSIM3v3 has been widely accepted as a standard CMOS model for low frequency applications. Recent work has demonstrated the capability of modeling CMOS devices at high frequencies by utilizing a complicated substrate resistance network and extensive modification to the BSIM3v3 source code. This paper first describes a unified device model realized with a lumped resistance network suitable for simulations of both RF and baseband analog circuits; then verifies the accuracy of the model to measured data on both device and circuit levels.
103 citations
"Design and analysis for a miniature..." refers background in this paper
...A large-signal field-effect transistor (FET) model of a passive high electron-mobility transistor (HEMT) for the switch circuit was presented [10], and the power performance of the series-shunt switch can be predicted accurately in the heterojunction field-effect transistor (HJFET)…...
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05 Feb 2001
TL;DR: A 4.5/spl times/4 mm/sup 2/ single-chip Bluetooth RF transceiver in a 0.35 /spl mu/m standard CMOS technology with minimal external components operates from a 3 V supply.
Abstract: A 4.5/spl times/4 mm/sup 2/ single-chip Bluetooth RF transceiver in a 0.35 /spl mu/m standard CMOS technology with minimal external components operates from a 3 V supply. The low-IF receiver achieves -77 dBm sensitivity for 0.1% BER and -17 dBm llP3. The direct up-conversion transmitter has 0 dBm nominal output power.
97 citations