Design and Analysis of Varactor-Less Interpolative-Phase-Tuning Millimeter-Wave LC Oscillators with Multiphase Outputs
TL;DR: The interpolative-phase-tuning (IPT) technique is proposed to tune the frequency of millimeter-wave (MMW) LC-based ring oscillators without using varactor, which makes the IPT technique suitable for applications at MMW frequencies.
Abstract: An interpolative-phase-tuning (IPT) technique is proposed to tune the frequency of millimeter-wave (MMW) LC-based ring oscillators without using varactor. As a key feature, the tradeoff between tank Q and tuning range of the proposed IPT oscillators is independent of the operation frequency, which makes the IPT technique suitable for applications at MMW frequencies. Moreover, the IPT oscillators can achieve larger frequency tuning range and much better phase accuracy over the tuning range as compared to the conventional gm-coupled LC oscillators for multiphase generation. Two IPT oscillator prototypes are designed and implemented in a 0.13-μm CMOS process. The first one operates at 50 GHz with eight output phases and measures phase noise of -103.7 dBc/Hz at 1-MHz offset and -127.8 dBc/Hz at 10-MHz offset, tuning range of 6.8%, and figure of merit (FOM) of 186.4 dB while occupying chip area of 0.36 mm2. The second prototype oscillates at 60 GHz with four output phases and measures phase noise of -95.5 dBc/Hz at 1-MHz offset, -120.6 dBc/Hz at 10-MHz offset, tuning range of 9%, and FOM of 180.6 dB with chip area of 0.2 mm2.
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TL;DR: Using this novel frequency tuning method, two high-power terahertz VCOs are fabricated in a 65 nm LP bulk CMOS process and the output power of these signal sources is 4 orders of magnitude higher than previous CMOS V COs and is even higher thanVCOs implemented in compound semiconductors with much higher cut-off frequencies.
Abstract: We introduce a novel frequency tuning method for high-power terahertz sources in CMOS. In this technique, multiple core oscillators are coupled to generate, combine, and deliver their harmonic power to the output node without using varactors. By exploiting the theory of nonlinear dynamics, we control the coupling between the cores to set their phase shift and frequency. Using this method, two high-power terahertz VCOs are fabricated in a 65 nm LP bulk CMOS process. The first one has a measured output power of 0.76 mW at 290 GHz with 4.5% tuning range and the output power of the second VCO is 0.46 mW at 320 GHz with 2.6% tuning range. The output power of these signal sources is 4 orders of magnitude higher than previous CMOS VCOs and is even higher than VCOs implemented in compound semiconductors with much higher cut-off frequencies.
107 citations
Cites background from "Design and Analysis of Varactor-Les..."
...Both of these techniques still require additional active devices inside the oscillator tank....
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TL;DR: A switched-triple-shielded transformer is proposed to change the magnetic coupling coefficient between the primary and secondary coils in the transformer tank to greatly increase the frequency tuning range of the dual-band VCO to cover the whole E-band continuously.
Abstract: This paper presents a magnetically tuned (MT) multimode VCO featuring an ultrawide frequency tuning range. A switched-triple-shielded transformer is proposed to change the magnetic coupling coefficient between the primary and secondary coils in the transformer tank to greatly increase the frequency tuning range of the dual-band VCO to cover the whole E-band continuously. Fabricated in a 65-nm CMOS process, the MT-VCO measures a frequency tuning range of 41.1% from 57.5 to 90.1 GHz while consuming 7 to 9 mA at 1.2-V supply with chip area of 0.03 mm2. The measured phase noises at 10-MHz offset from carrier frequencies of 58, 72.2, 80.5, and 90.1 GHz, are -107.4, -111.8, -107.8, and -105.1 dBc/Hz, respectively, which correspond to FOMT between -184.2 and -192.2 dBc/Hz.
83 citations
TL;DR: In this article, a variable inductance seen at the emitter node of a base-degenerated transistor was used to achieve high quality factor and high tuning range due to the tunable transistor transconductance via bias current.
Abstract: A highly efficient push-push voltage-controlled oscillator (VCO) with a new inductive frequency tuning topology for (sub) terahertz frequencies is presented. The tuning technique is based on a variable inductance seen at the emitter node of a base-degenerated transistor. The variable inductor exhibits high quality factor and high tuning range due to the tunable transistor transconductance via bias current. Fabricated in a 0.13- μm SiGe BiCMOS process, the VCO achieves a tuning range of 3.5% and an output power of -7.2 dBm at 201.5 GHz. The dc power consumption of the VCO is 30 mW, resulting in a high dc to RF power efficiency of 0.6% and a figure of merit (FoMT) of -165, which is the highest FoM for any silicon-based VCO reported to date at this frequency range. To demonstrate the functionality of the tuning technique, three VCO prototypes at different oscillation frequencies, including one operating in the 222.7-229-GHz range, are implemented and measured.
54 citations
Cites background from "Design and Analysis of Varactor-Les..."
...The tuning range of this transformer-coupled inductance is determined by the mutual inductance and the primary and secondary windings’ current ratio which degrades at high frequency....
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TL;DR: A phase noise analysis for distributed oscillators based on impulse-sensitivity functions (ISF) is introduced and applied to study the proposed oscillator and arrays of it.
Abstract: An array of distributed oscillators for millimeter-wave phased arrays combines local oscillator (LO) generation and distribution, leading to a phase noise improvement proportional to the number of array elements. The unit “hybrid wave” oscillator (HWO) consists of a rotary traveling-wave oscillator with quadrature outputs, coupled to the other units through standing-wave oscillators. A phase noise analysis for distributed oscillators based on impulse-sensitivity functions (ISF) is introduced and applied to study the proposed oscillator and arrays of it. A standalone oscillator and a 4-elements array implemented in a 65 nm CMOS technology have a measured phase noise of -125 dBc/Hz and -131 dBc/Hz respectively at 10 MHz from the 52 GHz carrier. Each unit consumes 36 mW corresponding to a FoM of -183.7 dBc/Hz. The tuning range is from 51.9 to 56.5 GHz.
45 citations
Cites methods from "Design and Analysis of Varactor-Les..."
...The performances of the proposed HWO are compared with state-of-the-art quadrature and multiple output oscillators [4], [10], [26]–[31] in Table II....
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TL;DR: A fast-wakeup bang-bang LC digital phase-locked loop (DPLL) suitable for low-power wireline applications is presented and achieves a 40-reference-cycle lock time and a 16% tuning range while producing an 8-phase output clock with less than 2° quadrature phase error up to 25 GHz.
Abstract: A fast-wakeup bang-bang LC digital phase-locked loop (DPLL) suitable for low-power wireline applications is presented. The PLL uses a novel oscillator design to generate eight output phases using magnetic coupling. The fast-wakeup feature improves power efficiency by allowing PLL power-cycling while accommodating latency requirements. Fast lock upon wakeup is achieved by calibrating the phase of the feedback clock with respect to the reference clock using a first-order loop and is further assisted by on-the-fly adjustment of loop parameters. The eight-phase output clock is generated using a loop of four digitally-controlled oscillators (DCOs) that are magnetically coupled through a passive structure. This structure enables magnetic coupling among oscillators with 2x area improvement over the prior art. As a result, in addition to eliminating the noise and parasitic capacitance of active coupling devices, the compact design reduces parasitic wiring capacitance, which is a significant limitation in high-frequency coupled oscillator design. Implemented in a 40 nm CMOS technology, the design achieves a 40-reference-cycle (100 ns) lock time and a 16% tuning range while producing an 8-phase output clock with less than 2° quadrature phase error up to 25 GHz. Measured PLL jitter is 392 fs (integrated from 100 kHz to 100 MHz) at 25 GHz while drawing 64 mW of power, 23 mW of which is consumed in the multiphase DCO. The DPLL occupies a total area of 0.1 mm 2 .
35 citations
References
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01 Feb 1966
2,440 citations
"Design and Analysis of Varactor-Les..." refers methods in this paper
...Considering all of the above, the phase noise of an -stage IPT LC oscillator can be expressed by simply modifying the well-known Leeson equation [19] as...
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TL;DR: The issues and tradeoffs in the design and monolithic implementation of direct-conversion receivers are described and circuit techniques that can alleviate the drawbacks of this architecture are proposed.
Abstract: This paper describes the issues and tradeoffs in the design and monolithic implementation of direct-conversion receivers and proposes circuit techniques that can alleviate the drawbacks of this architecture. Following a brief study of heterodyne and image-reject topologies, the direct-conversion architecture is introduced and effects such as dc offset, I/Q mismatch, even-order distortion, flicker noise, and oscillator leakage are analyzed. Related design techniques for amplification and mixing, quadrature phase calibration, and baseband processing are also described.
1,289 citations
"Design and Analysis of Varactor-Les..." refers background in this paper
...IQ LO signals are also the prerequisites in image-rejection receivers [1]....
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08 Feb 1996
TL;DR: In this article, the authors present a 900 MHz oscillator circuit implemented in 1 /spl mu/m CMOS that affords modestly low-phase noise, has variable frequency with large output swing, and provides quadrature-phase outputs from two identical coupled oscillators, connected in such a way that they exert a mutual squelch when their relative phase is not in Quadrature.
Abstract: The local oscillator (LO) in a wireless transceiver satisfies many exacting requirements. A variable frequency enables a phase-locked loop (PLL) to servo the LO to a stable lower frequency reference, or to correct frequency errors from measurements on the received signal. A low phase noise ensures little interference with nearby channels. A large LO voltage-swing means that it can drive a mixer with greater linearity. Finally, in single-sideband applications, the LO must supply precise quadrature phases. Low phase noise mandates use of a high-Q resonator to tune the LO, although most RF resonators are usually not integrable on ICs. Quadrature outputs are usually derived from RC phase-shift of a single-phase LO output, but this is susceptible to component inaccuracy and loss in LO amplitude. The authors present a 900 MHz oscillator circuit implemented in 1 /spl mu/m CMOS that affords modestly low-phase noise, has variable frequency with large output swing, and provides quadrature-phase outputs from two identical coupled oscillators, connected in such a way that they exert a mutual squelch when their relative phase is not in quadrature. The coupled oscillators synchronize to exactly the same frequency, in spite of mismatches in their resonant circuits.
601 citations
"Design and Analysis of Varactor-Les..." refers background in this paper
...With , it is a popular topology to generate IQ signals [9], [14]–[17]....
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TL;DR: A novel fully differential frequency tuning concept is introduced to ease high integration of VCOs with quadrature outputs and leads to a cross-coupled double core LC-VCO as the optimal solution in terms of power consumption.
Abstract: This paper describes the design and optimization of VCOs with quadrature outputs. Systematic design of fully integrated LC-VCOs with a high inductance tank leads to a cross-coupled double core LC-VCO as the optimal solution in terms of power consumption. Furthermore, a novel fully differential frequency tuning concept is introduced to ease high integration. The concepts are verified with a 0.25-/spl mu/m standard CMOS fully integrated quadrature VCO for zero- or low-IF DCS1800, DECT, or GSM receivers. At 2.5-V power supply voltage and a total power dissipation of 20 mW, the quadrature VCO features a worst-case phase noise of -143 dBc/Hz at 3-MHz frequency offset over the tuning range. The oscillator is tuned from 1.71 to 1.99 GHz through a differential nMOS/pMOS varactor input.
454 citations
TL;DR: This paper describes the design of CMOS millimeter-wave voltage controlled oscillators and shows the lumped element approach can be used even for VCOs operating near 100-GHz and it results a smaller circuit area.
Abstract: This paper describes the design of CMOS millimeter-wave voltage controlled oscillators. Varactor, transistor, and inductor designs are optimized to reduce the parasitic capacitances. An investigation of tradeoff between quality factor and tuning range for MOS varactors at 24 GHz has shown that the polysilicon gate lengths between 0.18 and 0.24 /spl mu/m result both good quality factor (>12) and C/sub max//C/sub min/ ratio (/spl sim/3) in the 0.13-/spl mu/m CMOS process used for the study. The components were utilized to realize a VCO operating around 60 GHz with a tuning range of 5.8 GHz. A 99-GHz VCO with a tuning range of 2.5 GHz, phase noise of -102.7 dBc/Hz at 10-MHz offset and power consumption of 7-15mW from a 1.5-V supply and a 105-GHz VCO are also demonstrated. This is the CMOS circuit with the highest fundamental operating frequency. The lumped element approach can be used even for VCOs operating near 100-GHz and it results a smaller circuit area.
216 citations
"Design and Analysis of Varactor-Les..." refers background in this paper
...This would unfortunately increase the parasitic capacitance of the varactors and reduce their effective tuning ratio [4]....
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