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Journal ArticleDOI

Design and Characterization of High-Temperature ECL-Based Bipolar Integrated Circuits in 4H-SiC

10 Feb 2012-IEEE Transactions on Electron Devices (Institute of Electrical and Electronics Engineers (IEEE))-Vol. 59, Iss: 4, pp 1076-1083
TL;DR: In this article, the performance of low-voltage 4H-SiC n-p-n bipolar transistors and digital integrated circuits based on emitter-coupled logic is demonstrated.
Abstract: Operation up to 300 °C of low-voltage 4H-SiC n-p-n bipolar transistors and digital integrated circuits based on emitter-coupled logic is demonstrated. Stable noise margins of about 1 V are reported for a two-input or- nor gate operated on - 15 V supply voltage from 27 °C up to 300 °C. In the same temperature range, an oscillation frequency of about 2 MHz is also reported for a three-stage ring oscillator.
Citations
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Journal ArticleDOI
TL;DR: In this article, the performance of low-voltage 4H-SiC n-p-n bipolar transistors and digital integrated circuits based on emitter coupled logic is reported from -40 °C to 500 °C.
Abstract: Successful operation of low-voltage 4H-SiC n-p-n bipolar transistors and digital integrated circuits based on emitter coupled logic is reported from -40 °C to 500 °C. Nonmonotonous temperature dependence (previously predicted by simulations but now measured) was observed for the transistor current gain; in the range -40 °C-300 °C it decreased when the temperature increased, while it increased in the range 300 °C-500 °C. Stable noise margins of ~ 1 V were measured for a 2-input OR/NOR gate operated on -15 V supply voltage from 0 °C to 500 °C for both OR and NOR output.

84 citations


Cites background or methods or result from "Design and Characterization of High..."

  • ...Two different metal stacks (Ni and Ni/Ti/Al for n- and p-type, respectively) were deposited, patterned, and annealed to form ohmic contacts to emitter, base, and collector layer (more details can be found in [7] and [8])....

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  • ...The nonmonotonous RC temperature dependence is the result of two opposing phenomena that influence the sheet resistance of the heavily doped collector layer [7] when the temperature rises: increase of dopant ionization degree and reduction of majority carrier mobility....

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  • ...Digital ICs were first reported based on transistor–transistor logic up to 355 °C [6], and more recently based on emitter coupled logic (ECL) [7]....

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  • ...Index Terms— Bipolar junction transistor (BJT), emitter coupled logic (ECL), high-temperature integrated circuits (ICs), OR/NOR gate, silicon carbide (SiC)....

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  • ...Device saturation is caused by the lateral flow of IC in the heavily doped collector layer, which constitutes the major contribution to the collector resistance RC [7]....

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Journal ArticleDOI
TL;DR: An overview of the gate and base drivers for SiC power transistors which have been proposed by several highly qualified scientists is shown and the basic operating principle of each driver along with their applicability and drawbacks are presented.
Abstract: Silicon carbide (SiC) power transistors have started gaining significant importance in various application areas of power electronics. During the last decade, SiC power transistors were counted not only as a potential, but also more importantly as an alternative to silicon counterparts in applications where high efficiency, high switching frequencies, and operation at elevated temperatures are targeted. Various SiC device designs have been proposed and excessive investigations in terms of simulation and experimental studies have shown their advantageous performance compared to silicon technology. On a system-level, however, the design of gate and base drivers for SiC power transistors is very challenging. In particular, a sophisticated driver design is not only associated with properly switching the transistor and decreasing the switching power losses, but also it must incorporate protection features, as well as comply with the electromagnetic compatibility. This paper shows an overview of the gate and base drivers for SiC power transistors which have been proposed by several highly qualified scientists. In particular, the basic operating principle of each driver along with their applicability and drawbacks are presented. For this overview, the three most successful SiC power transistors are considered: junction-field-effect transistors, bipolar-junction transistors, and metal-oxide-semiconductor field-effect transistors. Last but not least, future challenges on gate and base drivers design are also presented.

79 citations


Cites background from "Design and Characterization of High..."

  • ...analog circuits designed in SiC have already been shown [94], [166], [167], while several very promising research outcomes in terms of HT packaging have also been presented [10], [168]–...

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Journal ArticleDOI
TL;DR: In this article, a monolithic bipolar operational amplifier (opamp) fabricated in 4H-SiC technology is presented, which is used in an inverting negative feedback amplifier configuration.
Abstract: A monolithic bipolar operational amplifier (opamp) fabricated in 4H-SiC technology is presented. The opamp has been used in an inverting negative feedback amplifier configuration. Wide temperature ...

69 citations


Cites methods from "Design and Characterization of High..."

  • ...The Spice Gummel Poon (SGP) model based on extracted parameters at 25 °C and 225 °C from [14] are used to simulate the circuit...

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Journal ArticleDOI
TL;DR: In this article, a fully integrated linear voltage regulator in silicon carbide NPN bipolar transistor technology, operational from 25 °C up to 500 °C, is demonstrated for 15-mA load current.
Abstract: In this paper, we demonstrate a fully integrated linear voltage regulator in silicon carbide NPN bipolar transistor technology, operational from 25 °C up to 500 °C. For 15-mA load current, this regulator provides a stable output voltage with <2% variation in the temperature range 25 °C–500 °C. For both line and load regulations, degradation of 50% from 25 °C to 300 °C and improvement of 50% from 300 °C to 500 °C are observed. The transient response measurements of the regulator show robust behavior in the temperature range 25 °C–500 °C.

38 citations

Journal ArticleDOI
TL;DR: In this paper, the electron transport that occurs within the wurtzite phases of gallium nitride, aluminum oxide, indium oxide, and zinc oxide has been studied.
Abstract: Wide energy gap semiconductors are broadly recognized as promising materials for novel electronic and optoelectronic device applications. As informed device design requires a firm grasp of the material properties of the underlying electronic materials, the electron transport that occurs within the wide energy gap semiconductors has been the focus of considerable study over the years. In an effort to provide some perspective on this rapidly evolving and burgeoning field of research, we review analyzes of the electron transport within some wide energy gap semiconductors of current interest in this paper. In order to narrow the scope of this review, we will primarily focus on the electron transport that occurs within the wurtzite phases of gallium nitride, aluminum nitride, indium nitride, and zinc oxide in this review, these materials being of great current interest to the wide energy gap semiconductor community; indium nitride, while not a wide energy gap semiconductor in of itself, is included as it is often alloyed with other wide energy gap semiconductors, the resultant alloys being wide energy gap semiconductors themselves. The electron transport that occurs within zinc-blende gallium arsenide is also considered, albeit primarily for bench-marking purposes. Most of our discussion will focus on results obtained from our ensemble semi-classical three-valley Monte Carlo simulations of the electron transport within these materials, our results conforming with state-of-the-art wide energy gap semiconductor orthodoxy. A brief tutorial on the Monte Carlo electron transport simulation approach, this approach being used to generate the results presented herein, is also provided. Steady-state and transient electron transport results are presented. The evolution of the field, and a survey of the current literature, are also featured. We conclude our review by presenting some recent developments on the electron transport within these materials.

36 citations

References
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MonographDOI
01 Jan 2002
TL;DR: Zetterling, S.M.Ostling and S.J.Pearton as mentioned in this paper, S.Sveinbjornsson, S.-K.Lee, and M.
Abstract: Introduction 1 Advantages of SiC C.-M.Zetterling and M.Ostling 2 Bulk and epitaxial growth of SiC N.Nordell 3 Ion implantation and diffusion in SiC A.Schoner 4 Wet and dry etching of SiC S.J.Pearton 5 Thermally grown and deposited thermoelectrics E.O.Sveinbjornsson and C.-M.Zetterling 6 Schottky and ohmic contacts to SiC C.-M.Zetterling, S.-K.Lee and M.Ostling 7 Devices in SiC C.-M.Zetterling, S.M.Koo and M.Ostling Appendix 1: Other resources Appendix 2: Glossary Index

218 citations


"Design and Characterization of High..." refers background in this paper

  • ...high-temperature applications because of its high critical field strength and thermal conductivity [1]....

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Journal ArticleDOI
TL;DR: In this article, the development of extreme temperature (up to 500 °C) integrated circuit technology based on epitaxial 6H-SiC junction field effect transistors (JFETs) is discussed.
Abstract: Extreme temperature semiconductor integrated circuits (ICs) are being developed for use in the hot sections of aircraft engines and other harsh-environment applications well above the 300 °C effective limit of silicon-on-insulator IC technology. This paper reviews progress by the NASA Glenn Research Center and Case Western Reserve University (CWRU) in the development of extreme temperature (up to 500 °C) integrated circuit technology based on epitaxial 6H-SiC junction field effect transistors (JFETs). Simple analog amplifier and digital logic gate ICs fabricated and packaged by NASA have now demonstrated thousands of hours of continuous 500 °C operation in oxidizing air atmosphere with minimal changes in relevant electrical parameters. Design, modeling, and characterization of transistors and circuits at temperatures from 24 °C to 500 °C are also described. CWRU designs for improved extreme temperature SiC JFET differential amplifier circuits are demonstrated. Areas for further technology maturation, needed prior to beneficial system insertion, are discussed. Optical micrograph of a 500 °C durable 6H-SiC JFET differential amplifier IC chip fabricated at NASA prior to packaging. Digitized waveforms measured during the 1st (solid black) and 6519th (dashed grey) hour of 500 °C operational testing show no change in output characteristics.

136 citations


"Design and Characterization of High..." refers background in this paper

  • ...Long-term stability of JFET ICs, both analog and digital, has been demonstrated in 6H-SiC with circuit operation at 500 ◦C for thousand hours [2]....

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Journal ArticleDOI
TL;DR: In this paper, the development of a 15V SiC CMOS technology developed to operate at high temperatures, n and p-channel transistor and preliminary circuit performance over temperature achieved in this technology.
Abstract: The wide band-gap of Silicon Carbide (SiC) makes it a material suitable for high temperature integrated circuits [1], potentially operating up to and beyond 450°C. This paper describes the development of a 15V SiC CMOS technology developed to operate at high temperatures, n and p-channel transistor and preliminary circuit performance over temperature achieved in this technology.

82 citations

Journal ArticleDOI
TL;DR: In this article, an implanted p-well process was used to construct the first 6H-SiC CMOS circuit with a 5V power supply for temperatures ranging from room temperature up to 300/spl deg/C.
Abstract: A CMOS technology in 6H-SiC utilizing an implanted p-well process is developed. The p-wells are fabricated by implanting boron ions into an n-type epilayer. PMOS devices are fabricated on an n-type epilayer while the NMOS devices are fabricated on implanted p-wells using a thermally grown gate oxide. The resulting NMOS devices have a threshold voltage of 3.3 V while the PMOS devices have a threshold voltage of -4.2 V at room temperature. The effective channel mobility is around 20 cm/sup 2//Vs for the NMOS devices and around 7.5 cm/sup 2//Vs for the PMOS devices. Several digital circuits, such as inverters, NAND's, NOR's, and 11-stage ring oscillators are fabricated using these devices and exhibited stable operation at temperatures ranging from room temperature to 300/spl deg/C. These digital circuits are the first CMOS circuits in 6H-SiC to operate with a 5-V power supply for temperatures ranging from room temperature up to 300/spl deg/C.

80 citations


"Design and Characterization of High..." refers background in this paper

  • ...CMOS technology has been investigated since early 1990s in 6H-SiC [3] and has been recently reported in 4H-SiC [4]....

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Journal ArticleDOI
TL;DR: In this article, the performance of bipolar junction transistor (BJT) is compared experimentally and by device simulation for 4H-SiC BJTs passivated with different surface passivation layers.
Abstract: In this brief, the electrical performance in terms of maximum current gain and breakdown voltage is compared experimentally and by device simulation for 4H-SiC BJTs passivated with different surface-passivation layers. Variation in bipolar junction transistor (BJT) performance has been correlated to densities of interface traps and fixed oxide charge, as evaluated through MOS capacitors. Six different methods were used to fabricate SiO2 surface passivation on BJT samples from the same wafer. The highest current gain was obtained for plasma-deposited SiO2 which was annealed in N2O ambient at 1100°C for 3 h. Variations in breakdown voltage for different surface passivations were also found, and this was attributed to differences in fixed oxide charge that can affect the optimum dose of the high-voltage junction-termination extension (JTE). The dependence of breakdown voltage on the dose was also evaluated through nonimplanted BJTs with etched JTE.

73 citations


"Design and Characterization of High..." refers methods in this paper

  • ...step was performed in order to provide low resistive ohmic contact to the epitaxial layer [7], [10]....

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  • ...After sacrificial oxidation in N2O ambient, surface passivation was performed with 50-nm PECVD SiO2 followed by postoxide anneal in N2O at 1150 ◦C for 3 h [10] in order to minimize surface recombination....

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