Design and Characterization of High-Temperature ECL-Based Bipolar Integrated Circuits in 4H-SiC
Citations
84 citations
Cites background or methods or result from "Design and Characterization of High..."
...Two different metal stacks (Ni and Ni/Ti/Al for n- and p-type, respectively) were deposited, patterned, and annealed to form ohmic contacts to emitter, base, and collector layer (more details can be found in [7] and [8])....
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...The nonmonotonous RC temperature dependence is the result of two opposing phenomena that influence the sheet resistance of the heavily doped collector layer [7] when the temperature rises: increase of dopant ionization degree and reduction of majority carrier mobility....
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...Digital ICs were first reported based on transistor–transistor logic up to 355 °C [6], and more recently based on emitter coupled logic (ECL) [7]....
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...Index Terms— Bipolar junction transistor (BJT), emitter coupled logic (ECL), high-temperature integrated circuits (ICs), OR/NOR gate, silicon carbide (SiC)....
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...Device saturation is caused by the lateral flow of IC in the heavily doped collector layer, which constitutes the major contribution to the collector resistance RC [7]....
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79 citations
Cites background from "Design and Characterization of High..."
...analog circuits designed in SiC have already been shown [94], [166], [167], while several very promising research outcomes in terms of HT packaging have also been presented [10], [168]–...
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69 citations
Cites methods from "Design and Characterization of High..."
...The Spice Gummel Poon (SGP) model based on extracted parameters at 25 °C and 225 °C from [14] are used to simulate the circuit...
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38 citations
36 citations
References
218 citations
"Design and Characterization of High..." refers background in this paper
...high-temperature applications because of its high critical field strength and thermal conductivity [1]....
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136 citations
"Design and Characterization of High..." refers background in this paper
...Long-term stability of JFET ICs, both analog and digital, has been demonstrated in 6H-SiC with circuit operation at 500 ◦C for thousand hours [2]....
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82 citations
80 citations
"Design and Characterization of High..." refers background in this paper
...CMOS technology has been investigated since early 1990s in 6H-SiC [3] and has been recently reported in 4H-SiC [4]....
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73 citations
"Design and Characterization of High..." refers methods in this paper
...step was performed in order to provide low resistive ohmic contact to the epitaxial layer [7], [10]....
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...After sacrificial oxidation in N2O ambient, surface passivation was performed with 50-nm PECVD SiO2 followed by postoxide anneal in N2O at 1150 ◦C for 3 h [10] in order to minimize surface recombination....
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