Design and FPGA implementation of flexible and efficiency digital down converter
03 Dec 2010-pp 438-441
TL;DR: The paper designed and implemented DDC with above advantages on Xilinx FPGA Virtex-5 on the basis of key points of DDC theory and MATLAB simulation analysis and designs one application of D DC in communication systems.
Abstract: Digital down converter (DDC) is the one of the key technologies in the field of software define radio (SDA). Compared with traditional ASIC DDC devices, DDCs implemented by FPGA have more flexible frequency and phase characteristics and higher precision computation. The paper designed and implemented DDC with above advantages on Xilinx FPGA Virtex-5. Through analyzing the key points of DDC theory and MATLAB simulation analysis, DDC with across clock region and FIFO interface characteristics is designed using Xilinx ISE. Some important and practical implementation details are given in this paper. And finally presents one application of DDC in communication systems by the portions given in this document.
Citations
More filters
01 Jan 2017
TL;DR: This study confirms that the wireless communication system for secured transmit data, fast and inexpensive; can be done by implementing using Partial Reconfiguration (PR) modern technology in FPGA developing based on SDR.
Abstract: Software Defined Radio (SDR) has the flexibility to modify the characteristics of the receiving and transmitting radio device, without physically adjusting the hardware, due to development in the system Because of the increasing need for wireless communication applications so as to enable consumers to communicate anywhere through information led to the emergence of many communication devices to include the large amount of applications that every one of the devices needs power and thereby increase the total power This study confirms that the wireless communication system for secured transmit data, fast and inexpensive; can be done by implementing using Partial Reconfiguration (PR) modern technology in FPGA developing based on SDR The Speed and performance can be improved The area also can be decreased The new Xilinx, Vertex Series FPGA, provides the provision of PR The power consumption can be reduced by applying power reduction techniques in the blocks The combination of MATLAB (Simulink and M-file) and Simulink HDL Coder offers flexible capabilities for analysis, design; simulation, implementation, and verification With all these capabilities, in a single system to reduce the time spent tuning for reducing the algorithms and models during rapid prototyping and experimentation and less time on HDL coding
7 citations
Additional excerpts
...[38] provides design and implementation of digital down converter on Xilinx Virtex-5,...
[...]
02 Mar 2018
TL;DR: A reconfigurable ddc architecture is introduced which reduces the hardware resources used and consists of a mixer, decimator and a FIR filter and is proposed on FPGA using Verilog or VHDL code.
Abstract: With the rapid growth in the technology, the generations that are evolved involve 1G, 2G,3G, 4G and 5G technologies. The Digital Down Converter (DDC) is one of the important parts of a 4G receiver system. Development of an efficient DDC architecture is highly important becausethe applications are increasingly demanding for high efficiency and less power consumption. Inthis paper, a reconfigurable ddc architecture is introduced which reduces the hardware resources used. It consists of a mixer, decimator and a FIR filter. The proposed architecture is compared with the existing architecture. Simulations can be performed using MATLAB and implementation is proposed on FPGA using Verilog or VHDL code. Verilog is widely used since it is user friendly and easily understandable. The proposed DDC reduces the gate density.
4 citations
Cites background or methods from "Design and FPGA implementation of f..."
...Therefore, the way to optimize for gate density, speed and efficiency is a vital issue for the look of DDC [2]....
[...]
...To resolve this issue a reconfigurable optimized multiphase DDC is designed and mixers are combined into the used polyphase decimation filter [2]....
[...]
01 Aug 2015
TL;DR: The technique involved in designing the filter is the usage of a special type of multiplier called Computation sharing multiplier(CSHM) which enhances the performance of the DDC and also reduces the component utilization in FPGA.
Abstract: In the field of software defined radio, DDC plays a pivotal role in defining the optimum sampling rate without encountering any loss of information The essential part of any DDC is the low pass filtering operation Traditionally CIC filters are used for the design of low pass filters in the DDC which poses disadvantages in the area occupied and delay in the FPGA devices This paper focuses on the shared resource technique for the design of the FIR filter operation The technique involved in designing the filter is the usage of a special type of multiplier called Computation sharing multiplier(CSHM) This technique enhances the performance of the DDC and also reduces the component utilization in FPGA Xilinx ISE is used to simulate and synthesize the design
4 citations
TL;DR: Experimental results demonstrate that the DDC achieves significant improvements on the GPU; the maximum speed ups in numerically controlled oscillator stage, CIC stage, and FIR stage can achieve more than 1242, 527, and 179 times, including data‐transfer, kernel execution, and other processing operations.
Abstract: Summary
Digital down converter (DDC) is a time-intensive and data-intensive computing task and considered as the key technology in software defined radio. This paper proposes a high-performance implementation of DDC on a graphics processing unit (GPU) using CUDA, which is composed of a numerically controlled oscillator stage, a cascaded integrator-comb (CIC) decimation filter stage, and a finite impulse response (FIR) filter stage. The GPU implementation and optimizing of all the stages are studied in detail. Additionally, for handling a long-duration signal, the signal data sequence is truncated into segments; the overlap-save and overlap-add mechanisms were applied in CIC stage and FIR stage, respectively. Finally, experiments were conducted to evaluate the performance of GPU-based DDC with respect to a sequential version CPU implementation and an OpenMP implementation (16 threads). Experimental results demonstrate that the DDC achieves significant improvements on the GPU; the maximum speed ups in numerically controlled oscillator stage, CIC stage, and FIR stage can achieve more than 1242, 527, and 179 times, including data-transfer, kernel execution, and other processing operations; the overall speed up of DDC can achieve more than 180. In the meantime, the speed ups of GPU implementation are far above the OpenMP implementation (about 2.5-6.4 times).
3 citations
01 Jan 2013
TL;DR: The design and implementation of Software Defined Radio (SDR) transceiver based 16-QAM as one of the key techniques in structure of wireless and mobile communication system and results shows the system capability to transmit and receive intermediate frequency of 40 MHZ keeping the power under limited FPGA Slices and look up table (LUT).
Abstract: This paper presents the design and implementation of Software Defined Radio (SDR) transceiver based 16-QAM as one of the key techniques in structure of wireless and mobile communication system. The widely used of QAM in adaptive modulation due to efficient power and bandwidth force the researchers to found better and easy design by use the available software like MATLAB in order to advance the idea of software defined radio. The setting of parameter for random generator, QAM modulation and demodulation, AWGN wireless channel are provided. The Error rates of QAM system against the signal-to-noise ratio are used to evaluate the QAM system. The implementation results shows the system capability to transmitand receive intermediate frequency of 40 MHZ keeping the power under limited FPGA Slices and look up table (LUT).
2 citations
References
More filters
TL;DR: A closer look at the canonical functional partitioning of channel coding into antenna, RF, IF, baseband, and bitstream segments and a brief treatment of the economics and likely future directions of software radio technology are provided.
Abstract: As communications technology continues its rapid transition from analog to digital, more functions of contemporary radio systems are implemented in software, leading toward the software radio. This article provides a tutorial review of software radio architectures and technology, highlighting benefits, pitfalls, and lessons learned. This includes a closer look at the canonical functional partitioning of channel coding into antenna, RF, IF, baseband, and bitstream segments. A more detailed look at the estimation of demand for critical resources is key. This leads to a discussion of affordable hardware configurations, the mapping of functions to component hardware, and related software tools. This article then concludes with a brief treatment of the economics and likely future directions of software radio technology. >
2,002 citations
"Design and FPGA implementation of f..." refers background in this paper
...With their inherent parallelism and the growing libraries of IP cores available, it is practical and efficient to design DDCs based on FPGAs, especially narrowband and high channel count DDCs. [3][4][5] Taking advantage of design flexibility, high precision computing and system-level resource…...
[...]
01 Jan 2002
TL;DR: In this article, the basic operations of these filter banks are considered and the requirements are stated for alias-free, perfect-reconstruction (PR), and nearly perfect reconstruction (NPR) filter banks.
Abstract: The outline of this chapter is as follows. Section 2 reviews various types of existing finite impulse response (FIR) and infinite impulse response (IIR) two-channel filter banks. The basic operations of these filter banks are considered and the requirements are stated for alias-free, perfect-reconstruction (PR), and nearly perfect-reconstruction (NPR) filter banks. Also some efficient synthesis techniques are referred to. Furthermore, examples are included to compare various two-channel filter banks with each other. Section 3 concentrates on the design of multi-channel (M-channel) uniform filter banks. The main emphasis is laid on designing these banks using tree-structured filter banks with the aid of two-channel filter banks and on generating the overall bank with the aid of a single prototype filter and a proper cosine-modulation or MDFT technique. In Section 4, it is shown how octave filter banks can be generated using a single two-channel filter bank as the basic building block. Also, the relations between the frequency-selective octave filter banks and discrete-time wavelet banks are briefly discussed. Finally, concluding remarks are given in Section 5.
1,598 citations
"Design and FPGA implementation of f..." refers background in this paper
...The unwanted frequency components fall outside the pass bands of the filter....
[...]
Book•
01 May 1997
TL;DR: A number of new topics have been added to the second edition of "Digital Signal Processing: A Computer-Based Approach", based on user feedback, and the author has taken great care to organize the chapters more logically by reordering the sections within chapters.
Abstract: From the Publisher:
"Digital Signal Processing: A Computer-Based Approach" is intended for a two-semester course on digital signal processing for seniors or first-year graduate students. Based on user feedback,a number of new topics have been added to the second edition,while some excess topics from the first edition have been removed. The author has taken great care to organize the chapters more logically by reordering the sections within chapters. More worked-out examples have also been included. The book contains more than 500 problems and 150 MATLAB exercises. New topics in the second edition include: finite-dimensional discrete-time systems,correlation of signals,inverse systems,system identification,matched filter,design of analog and IIR digital highpass,bandpass and bandstop filters,more on FIR filters,spectral analysis of random signals and sparse antenna array design.
1,470 citations
Book•
20 May 2002
TL;DR: Software Radio: A Modern approach to Radio Engineering systematically reviews the techniques, challenges, and tradeoffs of DSP software radio design to help engineers build advanced wireless systems.
Abstract: Software-based approaches enable engineers to build wireless system radios that are easier to manufacture, more flexible, and more cost-effective. Software Radio: A Modern Approach to Radio Engineering systematically reviews the techniques, challenges, and tradeoffs of DSP software radio design. Coverage includes constructing RF front-ends; using digital processing to overcome RF design problems; direct digital synthesis of modulated waveforms; A/D and D/A conversions; smart antennas; object-oriented software design; and choosing among DSP microprocessors, FPGAs, and ASICs. This is an excellent book for all RF and signal processing engineers building advanced wireless systems.
502 citations
"Design and FPGA implementation of f..." refers background in this paper
...DDC is a technique that takes a band limited high sample rate digitized signal, mixes the signal to a lower frequency and reduces the sample rate while retaining all the information....
[...]
10 Dec 2008
TL;DR: FPGA-based Implementation of Signal Processing Systems is an important reference for practising engineers and researchers working on the design and development of DSP systems for radio, telecommunication, information, audio-visual and security applications.
Abstract: Field programmable gate arrays (FPGAs) are an increasingly popular technology for implementing digital signal processing (DSP) systems. By allowing designers to create circuit architectures developed for the specific applications, high levels of performance can be achieved for many DSP applications providing considerable improvements over conventional microprocessor and dedicated DSP processor solutions. The book addresses the key issue in this process specifically, the methods and tools needed for the design, optimization and implementation of DSP systems in programmable FPGA hardware. It presents a review of the leading-edge techniques in this field, analyzing advanced DSP-based design flows for both signal flow graph- (SFG-) based and dataflow-based implementation, system on chip (SoC) aspects, and future trends and challenges for FPGAs. The automation of the techniques for component architectural synthesis, computational models, and the reduction of energy consumption to help improve FPGA performance, are given in detail. Written from a system level design perspective and with a DSP focus, the authors present many practical application examples of complex DSP implementation, involving: high-performance computing e.g. matrix operations such as matrix multiplication; high-speed filtering including finite impulse response (FIR) filters and wave digital filters (WDFs); adaptive filtering e.g. recursive least squares (RLS) filtering; transforms such as the fast Fourier transform (FFT). FPGA-based Implementation of Signal Processing Systems is an important reference for practising engineers and researchers working on the design and development of DSP systems for radio, telecommunication, information, audio-visual and security applications. Senior level electrical and computer engineering graduates taking courses in signal processing or digital signal processing shall also find this volume of interest.
215 citations