Proceedings ArticleDOI
Design and implementation of 16×16 modified booth multiplier
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TLDR
This paper presents the design of 16*16 Modified Booth multiplier which performs both signed and unsigned multiplication and used Carry Select Adder it increases the speed of multiplier operation.Abstract:
The Modified Booth multiplier is attractive to many multimedia and digital signal processing systems. This paper presents the design of 16∗16 Modified Booth multiplier. The multipliers such as Braun array multiplier and Array multiplier are used for unsigned multiplication. This paper focusing on design of Modified Booth Multiplier which performs both signed and unsigned multiplication. Here used Carry Select Adder it increases the speed of multiplier operation. Booth encoder multiplier with Carry select Adder utilizes the minimum hardware, reduced chip area, low power dissipation and reduced the cost of the system.read more
Citations
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Journal ArticleDOI
Design of efficient quantum Dot cellular automata (QCA) multiply accumulate (MAC) unit with power dissipation analysis
TL;DR: The proposed circuit has 90% improvement in terms of power over complementary metal–oxide–semiconductor (CMOS) circuits and will give rise to a new thread of research in the field of real-time signal and image treatment.
Journal ArticleDOI
Low-Cost and High-Performance 8 × 8 Booth Multiplier
TL;DR: A power/delay/area performance-improved radix-4 8 × 8 Booth multiplier with major modification for reducing delay is a parallel structure for the addition of encoded partial products to minimize multiplier’s delay.
Journal ArticleDOI
An Efficient Single Precision Floating Point Multiplier Architecture based on Classical Recoding Algorithm
TL;DR: 32 bit improved FP multiplication based on classical recoding and parallel processing method is proposed and shows that the proposed design runs with high frequency with less resource utilization and suitable for signal processing applications.
Journal ArticleDOI
Area–Energy–Error Optimized Faithful Multiplier for Digital Signal Processing
Kalaiselvi Sundaram,Vijeyakumar Krishnasamy Natarajan,Nagarajan Shanmugam,Kousalya Manoharan,Ramya Ramasamy,Sriram Kumar +5 more
TL;DR: The design of a novel 4: 2 approximate compressor that generates no error in the carry signal is presented, and the proposed compressor is employed for partial product compression in two variants of Dadda multiplier to see its effectiveness in error-resilient image and signal processing applications.
Proceedings ArticleDOI
Exploring Approximate Computing and Near- Threshold Operation to Design Energy -efficient Multipliers
TL;DR: In this article, two approximate adders are adopted in the lower bits of a set of multiplier circuits to explore alternative approaches for energy-efficient scenarios, and the results show that by applying near-threshold operation, it is possible to achieve a considerable reduction in power consumption, however, with a significant increase in delay.
References
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Journal ArticleDOI
High-Speed Arithmetic in Binary Computers
TL;DR: Methods of obtaining high speed in addition, multiplication, and division in parallel binary computers are described and then compared with each other as to efficiency of operation and cost.
Journal ArticleDOI
Approximate Radix-8 Booth Multipliers for Low-Power and High-Performance Operation
TL;DR: The bit approximate radix-8 Booth multipliers are designed using the approximate recoding adder with and without the truncation of a number of less significant bits in the partial products.
Journal ArticleDOI
High-Accuracy Fixed-Width Modified Booth Multipliers for Lossy Applications
TL;DR: Experimental results on two real-life applications demonstrate that the proposed fixed-width modified Booth multipliers can improve the average peak signal-to-noise ratio of output images by at least 2.0 dB and 1.1 dB, respectively.
Journal ArticleDOI
Radix-4 and Radix-8 Booth Encoded Multi-Modulus Multipliers
TL;DR: Novel multi-modulus designs capable of performing the desired modulo operation for more than one modulus in Residue Number System (RNS) are explored in this paper to lower the hardware overhead of residue multiplication.
Low Power Floating Point Computation Sharing Multiplier for Signal Processing Applications
TL;DR: Experimental results on a 10-tap programmable FIR filter show that the proposed multiplier scheme can provide a power reduction of 39.7% and significant improvements in the performance compared to conventional floating-point carry save array multiplier implementations.