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Proceedings ArticleDOI

Design and implementation of a high speed Serial Peripheral Interface

19 Jun 2014-pp 1-3
TL;DR: The purpose of this paper is to provide a full description of a high speed SPI Master/Slave implementation based on Motorola's SPI Block Guide V03.06, and mapped onto Xilinx's Virtex 5 FPGA devices.
Abstract: Serial Peripheral Interface is a synchronous protocol that allows serial communication between a master and a slave device. The purpose of this paper is to provide a full description of a high speed SPI Master/Slave implementation. The designs are based on Motorola's SPI Block Guide V03.06. This paper discusses design approaches that can offer prospective ways of controlling SPI-bus, incorporating the flexibility of handling two slaves at a time. Starting from the initial specifications till the final physical design, the design phases are systematically elaborated. The whole design is implemented in Verilog 2001, and mapped onto Xilinx's Virtex 5 FPGA devices.
Citations
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Journal ArticleDOI
TL;DR: In this paper, a simulation methodology and an electromagnetic compatibility qualification environment (EQE) are developed to verify the electromagnetic susceptibility of semicustom digital integrated circuits (IC) during the design phase.
Abstract: In this paper, a simulation methodology and an electromagnetic compatibility qualification environment (EQE) are developed to verify the electromagnetic susceptibility of semicustom digital integrated circuits (IC) during the design phase. The immunity levels of the digital circuits are estimated by the functional failure and delay change caused by the external noise which is injected by bulk current injection (BCI) and direct power injection (DPI) methods. The model for the device under test (DUT), the standard cell parasitic model, and the equivalent circuit model of BCI and DPI test setup are developed for the IC immunity test. All test components and on-chip circuit models are linked by EQE to analyze the target DUT. The EQE can be applied to predict the immunity level of the design at the schematic level and postlayout level design. To validate the accuracy of the proposed simulation tool, EQE is applied to the design process of a clock divider (CKD) and a serial peripheral interface (SPI) circuits to verify their immunity levels. The CKD and SPI circuits are designed and fabricated using Magna 180 nm Complementary metal-oxide semiconductor (CMOS) technology. The immunity levels generated by the EQE are compared with the experimental measurement results. The comparison shows good agreement between simulation and measurement.

8 citations

Proceedings ArticleDOI
01 Apr 2017
TL;DR: The proposed approach is to acquire data from multiple channels of single data source into XILINX sparten-6 Field Programmable Gate Array (FPGA) followed by storing the same onto high speed storage device such as Static Random Access Memory (SRAM).
Abstract: A Data Acquisition System (DAQs) is an indispensable part to receive, store and further analysis of data. This paper focuses on Data Acquisition from multiple channels using Dual Data Rate (DDR) techniques. Multiple Channels of data source which are source synchronous are initially configured using Serial Peripheral Interface (SPI) commands. The Proposed technique gives an advantage of storing data received from multiple channels in parallel form. The proposed approach is divided into two parts. First is to acquire data from multiple channels of single data source into XILINX sparten-6 Field Programmable Gate Array (FPGA) followed by storing the same onto high speed storage device such as Static Random Access Memory (SRAM).

5 citations

Journal ArticleDOI
28 Aug 2020
TL;DR: SPI communication is implemented to expand the output of the Arduino Uno by using the features of the MCP23S17 IC so that theduino Uno, which initially has 20 output pins, can expand to 36 output pins.
Abstract: Serial Peripheral Interface (SPI) is a synchronous serial communication whose data or signal transmission involves Chip Select (CS) or Slave Select (SS) pins, Serial Clock (SCK), Master Out Slave In (MOSI), and Master In Slave Out (MISO). In the Arduino Uno, there are four pins that allow Arduino Uno to perform SPI communication. In this research, SPI communication is implemented to expand the output of the Arduino Uno by using the features of the MCP23S17 IC so that the Arduino Uno, which initially has 20 output pins, can expand to 36 output pins.The results of the research show that the Arduino Uno manages to control 36 output pins. 16 output pins from the MCP23S17, 16 output pins from the Arduino Uno, and 4 pins are used for the SPI communication line. The results of this study also show the form of the SPI communication signal from Arduino Uno in declaring 21 registers on MCP23S17, declaring the MCP23S17 pin register as output, and implementing the output using LEDs.

5 citations


Cites background from "Design and implementation of a high..."

  • ...SPI communication consists of masters and slaves [5], the master provides SCK to synchronize....

    [...]

01 Jan 2018
TL;DR: This paper discusses a Universal Verification Methodology based environment for testing a Wishbone compliant SPI master controller core and verification results shows the effectiveness and feasibility of the proposed verification environment.
Abstract: In today’s world, more and more functionalities in the form of IP cores are integrated into a single chip or SOC. System-level verification of such large SOCs has become complex. The modern trend is to provide pre-designed IP cores with companion Verification IP. These Verification IPs are independent, scalable, and reusable verification components. The SystemVerilog language is based on object-oriented principles and is the most promising language to develop a complete verification environment with functional coverage, constrained random testing and assertions. The Universal Verification Methodology, written in SystemVerilog, is a base class library of reusable verification components. This paper discusses a Universal Verification Methodology based environment for testing a Wishbone compliant SPI master controller core. A multi-layer testbench was developed which consists of a Wishbone bus functional model, SPI slave model, driver, scoreboard, coverage analysis, and assertions developed using various properties of SystemVerilog an the UVM library. Later, constrained random testing using vectors driven into the DUT for higher functional coverage is discussed. The verification results shows the effectiveness and feasibility of the proposed verification environment.

2 citations

Proceedings ArticleDOI
23 Mar 2016
TL;DR: This paper aims at design and development of a flexible reconfigurable SPI interface to configure the wide-band RF transceiver to overcome the disadvantage of non-programmability of discrete Commercial-Off-The-Shelf (COTS) RF components.
Abstract: Prototyping of wireless radio is very important to demonstrate the features of any wireless radio before deployment. The core implementation stages of wireless radio prototype include physical layer digital baseband (DBB) processing, RF transceiver chip configuration and interfacing of baseband and RF. Flexibility and adaptivity are very much required in MIMO-OFDM based realtime prototypes, which is considered a key technology in all modern wireless-access communication systems. Realizing flexible digital interface between DBB and RF transceiver in such prototypes is one of the important challenge. Furthermore, to overcome the disadvantage of non-programmability of discrete Commercial-Off-The-Shelf (COTS) RF components and also to reduce the time to prototype an efficient and flexible interfacing of Integrated RF module is required. These RF ICs are interfaced to digital baseband processor through Serial Peripheral Interface (SPI). This paper aims at design and development of a flexible reconfigurable SPI interface to configure the wide-band RF transceiver. The SPI IP core is implemented in VHDL and ported on Altera Cyclone-V FPGA to meet the timing and to do realtime control of RF transceiver.

2 citations


Cites methods from "Design and implementation of a high..."

  • ...The device combines a RF front end with a flexible mixed-signal baseband section, integrated frequency synthesizers and fully configurable through digital interface....

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References
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Journal ArticleDOI
F. Leens1
TL;DR: Today, at the low end of the communication protocols the authors find the inter-integrated circuit (I2C) and the serial peripheral interface (SPI) protocols, which are well suited for communications between integrated circuits for slow communication with on-board peripherals.
Abstract: Today, at the low end of the communication protocols we find the inter-integrated circuit (I2C) and the serial peripheral interface (SPI) protocols. Both protocols are well suited for communications between integrated circuits for slow communication with on-board peripherals. The two protocols coexist in modern digital electronics systems, and they probably will continue to compete in the future, as both I2C and SPI are actually quite complementary for this kind of communication.

224 citations


"Design and implementation of a high..." refers background in this paper

  • ...Ethernet, USB, and SATA are meant for “outside the box communications” and data exchanges between whole systems while SPI is aptly suited for communication between integrated circuits for low/medium data transfer speed with on-board peripherals [2], [3]....

    [...]

Proceedings ArticleDOI
01 Dec 2009
TL;DR: This paper contrasts and compares physical implementation aspects of the two protocols through a number of recent Xilinx FPGA families, showing up which protocol features are responsible of substantial area overhead.
Abstract: I2C and SPI are the most commonly used serial protocols for both inter-chip and intra-chip low/medium bandwidth data-transfers. This paper contrasts and compares physical implementation aspects of the two protocols through a number of recent Xilinx?s FPGA families, showing up which protocol features are responsible of substantial area overhead. This valuable information helps designers to make careful and tightly tailored architecture decisions. For a comprehensive comparative study, both protocols are implemented as general purpose IP solutions, incorporating all necessary features required by modern ASIC/SoC applications according to a recent market investigation of an important number of commercial I2C and SPI devices. The RTL code is technology independent, inducing around 25% area overhead for I2C over SPI, and almost the same delays for both designs.

63 citations


"Design and implementation of a high..." refers background in this paper

  • ...Ethernet, USB, and SATA are meant for “outside the box communications” and data exchanges between whole systems while SPI is aptly suited for communication between integrated circuits for low/medium data transfer speed with on-board peripherals [2], [3]....

    [...]

Proceedings ArticleDOI
27 Jun 2010
TL;DR: SPI is one of the most commonly used serial protocols for both inter-chip and intra-chip low/medium speed data-stream transfers.
Abstract: SPI is one of the most commonly used serial protocols for both inter-chip and intra-chip low/medium speed data-stream transfers.

25 citations


"Design and implementation of a high..." refers background in this paper

  • ...It is capable of receiving and transmitting on both rising and falling edges of the clock independently [1]....

    [...]

Proceedings ArticleDOI
15 Jul 2011
TL;DR: The test results indicate that the SPI interface controller's function and performance are all achieve design target, many communication tests indicate the design is reliable in performance.
Abstract: This paper describes a design and implementation of SPI interface model which is used for a SoC chip. The objective of this design is to realize expediently communicate between SoC chip and peripheral equipment. The paper analyses the sequence of SPI protocol, describes the design project of implement SPI logical function. Besides, the design is compatible with the SPI protocal and the function is also expanded, finally achieves powerful in function. After testbench and FPGA verification, the SoC chip that used this SPI model had been successfully processed. The test results indicate that the SPI interface controller's function and performance are all achieve design target, many communication tests indicate the design is reliable in performance.

8 citations

Proceedings ArticleDOI
M. Greco1, Maria Pia Bussa1, L. Ferrero1, M. Maggiora1, Andrea Verna2 
01 Oct 2011
TL;DR: The PANDA (antiProton ANnihilation in Darmstadt) experiment at the new Facility for Antiproton and Ion Research (FAIR) will study interactions between protons and antiprotons in the momentum range 1.5–15 GeV/c.
Abstract: The PANDA (antiProton ANnihilation in Darmstadt) experiment at the new Facility for Antiproton and Ion Research (FAIR) will study interactions between protons and antiprotons in the momentum range 1.5–15 GeV/c. The physics program is very demanding and requires an efficient and flexible triggering system that can handle a data rate in the range 40 to 200 GB / s due to an interaction rate of over 10 MHz.

2 citations