Proceedings ArticleDOI
Design and implementation of a high speed Serial Peripheral Interface
Anand N,George Joseph,Suwin Sam Oommen,R. Dhanabal +3 more
- pp 1-3
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TLDR
The purpose of this paper is to provide a full description of a high speed SPI Master/Slave implementation based on Motorola's SPI Block Guide V03.06, and mapped onto Xilinx's Virtex 5 FPGA devices.Abstract:
Serial Peripheral Interface is a synchronous protocol that allows serial communication between a master and a slave device. The purpose of this paper is to provide a full description of a high speed SPI Master/Slave implementation. The designs are based on Motorola's SPI Block Guide V03.06. This paper discusses design approaches that can offer prospective ways of controlling SPI-bus, incorporating the flexibility of handling two slaves at a time. Starting from the initial specifications till the final physical design, the design phases are systematically elaborated. The whole design is implemented in Verilog 2001, and mapped onto Xilinx's Virtex 5 FPGA devices.read more
Citations
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References
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Journal ArticleDOI
An introduction to I 2 C and SPI protocols
TL;DR: Today, at the low end of the communication protocols the authors find the inter-integrated circuit (I2C) and the serial peripheral interface (SPI) protocols, which are well suited for communications between integrated circuits for slow communication with on-board peripherals.
Proceedings ArticleDOI
FPGA implementation of I 2 C & SPI protocols: A comparative study
TL;DR: This paper contrasts and compares physical implementation aspects of the two protocols through a number of recent Xilinx FPGA families, showing up which protocol features are responsible of substantial area overhead.
Proceedings ArticleDOI
Design and test of general-purpose SPI Master/Slave IPs on OPB bus
TL;DR: SPI is one of the most commonly used serial protocols for both inter-chip and intra-chip low/medium speed data-stream transfers.
Proceedings ArticleDOI
The design and realization of a comprehensive SPI interface controller
TL;DR: The test results indicate that the SPI interface controller's function and performance are all achieve design target, many communication tests indicate the design is reliable in performance.
Proceedings ArticleDOI
VHDL implementation of a SPI controller for PANDA digital signal processing
TL;DR: The PANDA (antiProton ANnihilation in Darmstadt) experiment at the new Facility for Antiproton and Ion Research (FAIR) will study interactions between protons and antiprotons in the momentum range 1.5–15 GeV/c.