Design and implementation of low power dual edge triggered flip-flop using GDI and TG for high speed FIR filter
01 Mar 2017-pp 652-657
TL;DR: CAD tool based simulation and comparison between the non-conventional DET flip-flop with the conventional DETFF shows that the proposed DETFF reduces power dissipation by 66% reducing the no.
Abstract: In this paper, a technique for implementing low-power Dual Edge Triggered Flip Flop (DETFF) is introduced. Dual edge triggered flip flops has many advantages in low power VLSI compared to SETFF. The Proposed low power DETFF is implemented and compared with conventional DETFF at same simulation conditions. CAD tool based simulation and comparison between the non-conventional DET flip-flop with the conventional DETFF shows that the proposed DETFF reduces power dissipation by 66% reducing the no. of transistors used while keeping the same data rate.
Citations
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TL;DR: Comparison with some of the latest DETFFs shows that the proposed DETSFF can achieve the lowest power consumption, lowest clock to Q delay and thus Power-delay-product (PDP).
Abstract: In this paper a low-power double-edge triggered static flip-flop (DETSFF) suitable for low-power and high performance applications is presented. The designed DETFF is verified at gpdk 180nm-1.8V CMOS technology. Comparison with some of the latest DETFFs shows that the proposed DETSFF can achieve the lowest power consumption, lowest clock to Q delay and thus Power-delay-product (PDP). Moreover, the proposed DETSFF comprises of only 15 transistors hence require lesser number of transistors and thus requires lesser overall silicon area. DOI: http://dx.doi.org/10.11591/ijece.v3i5.3164
6 citations
4 citations
TL;DR: This paper addresses logic swing degradation in Gate Diffusion Input (GDI) and the glitches caused by the corresponding technique during run time and an EGDI based full adder with focus on EGDI logic cells and its realizations has been proposed.
3 citations
References
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Book•
01 Aug 1995
TL;DR: In this article, the authors provide rigorous treatment of basic design concepts with detailed examples for CMOS digital integrated circuits, including basic CMOS gates, interconnect effects, dynamic circuits, memory circuits, BiCMOS circuits, I/O circuits, VLSI design methodologies, low power design techniques, design for manufacturability and design for testability.
Abstract: CMOS Digital Integrated Circuits: Analysis and Design is the most complete book on the market for CMOS circuits. Appropriate for electrical engineering and computer science, this book starts with CMOS processing, and then covers MOS transistor models, basic CMOS gates, interconnect effects, dynamic circuits, memory circuits, BiCMOS circuits, I/O circuits, VLSI design methodologies, low-power design techniques, design for manufacturability and design for testability.
This book provides rigorous treatment of basic design concepts with detailed examples. It typically addresses both the computer-aided analysis issues and the design issues for most of the circuit examples. Numerous SPICE simulation results are also provided for illustration of basic concepts. Through rigorous analysis of CMOS circuits in this text, students will be able to learn the fundamentals of CMOS VLSI design, which is the driving force behind the development of advanced computer hardware.
Table of contents
1 Introduction
2 Fabrication of MOSFETS
3 MOS Transistor
4 Modeling of MOS Transistors Using SPICE
5 MOS Inverters: Static Characteristics
6 MOS Inverters: Switching Characteristics and Interconnect Effects
7 Combinational MOS Logic Circuits
8 Sequential MOS Logic Circuits
9 Dynamic Logic Circuits
10 Semiconductor Memories
11 Low-Power CMOS Logic Circuits
12 BiCMOS Logic Circuits
13 Chip Input and Output (I/O) Circuits
14 Design for Manufacturability
15 Design for Testability
888 citations
TL;DR: Gate diffusion input (GDI) - a new technique of low-power digital combinatorial circuit design - is described, showing advantages and drawbacks of GDI compared to other methods.
Abstract: Gate diffusion input (GDI) - a new technique of low-power digital combinatorial circuit design - is described. This technique allows reducing power consumption, propagation delay, and area of digital circuits while maintaining low complexity of logic design. Performance comparison with traditional CMOS and various pass-transistor logic design techniques is presented. The different methods are compared with respect to the layout area, number of devices, delay, and power dissipation. Issues like technology compatibility, top-down design, and precomputing synthesis are discussed, showing advantages and drawbacks of GDI compared to other methods. Several logic circuits have been implemented in various design styles. Their properties are discussed, simulation results are reported, and measurements of a test chip are presented.
299 citations
Proceedings Article•
01 Jan 1998
TL;DR: Simulation using SPICE and a 1 /spl mu/ technology shows that this proposed double-edge-triggered (DET) flip-flop has ideal logic functionality, a simpler structure, lower delay time, and higher maximum data rate compared to other existing CMOS DET flip- flops.
Abstract: The logic construction of a double-edge-triggered (DET) flip-flop, which can receive input signal at two levels of the clock, is analyzed and a new circuit design of CMOS DET flip-flop is proposed Simulation using SPICE and a 1 micron technology shows that this DET flip-flop has ideal logic functionality, a simpler structure, lower delay time and higher maximum data rate compared to other existing CMOS DET flipflops By simulating and comparing the proposed DET flip-flop with the traditional single-edge-triggered (SET) flip-flop, it is shown that the proposed DET flip-flop reduces power dissipation by half while keeping the same date rate
117 citations
TL;DR: A low-swing clock double-edge triggered flip-flop (LSDBF) is developed to reduce power consumption significantly compared to conventional FFs and avoids unnecessary internal node transition and reduces conflicting currents.
Abstract: A low-swing clock double-edge triggered flip-flop (LSDFF) is developed to reduce power consumption significantly compared to conventional flip-flops. The LSDFF avoids unnecessary internal node transitions to reduce power consumption. In addition, power consumption in the clock tree is reduced because LSDFF uses a double-edge triggered operation as well as a low-swing clock. To prevent performance degradation of the LSDFF due to low-swing clock, low-V/sub t/ transistors are used for the clocked transistors without significant leakage current problems. The power saving in flip-flop operation is estimated to be 28.6% to 49.6% with additional 78% power saving in the clock network.
87 citations