Design and Implementation of Power Optimized Dual Core and Single Core DLX Processor on FPGA
01 Jul 2018-pp 1-5
TL;DR: The aim of the work is to design and implement a low power 32 bits RISC core on Xilinx Nexys 4 FPGA and further reducing the dynamic power consumption by implementing a shared RAM dual core design and take advantage of parallelism offered by FPGAs to run two cores simultaneously.
Abstract: The aim of the work is to design and implement a low power 32 bits RISC core on Xilinx Nexys 4 FPGA. We also look at the further reducing the dynamic power consumption by implementing a shared RAM dual core design and take advantage of parallelism offered by FPGAs to run two cores simultaneously. The design is based on 5-stage pipelined DLX architecture. The DLX architecture in a RISC core consists of Fetch, Decode, Execute, Memory access and Write-back cycle. The core is designed using Verilog HDL. The standard low power single core design consumes 0.098W at 100MHz frequency. The shared RAM dual core design consumes 0.101W at 100MHz clock frequency. For this design we also code an assembler to convert Assembly language to machine code in python.
References
More filters
01 Jan 2006
TL;DR: The architecture and design of the pipelined execution unit of a 32-bit RISC processor, modeled in verilog HDL and functional verification policies adopted for it have been described thoroughly.
Abstract: The paperdescribes thearchitecture anddesign of thepipelined execution unitofa 32-bit RISC processor. Organization oftheblocks indifferent stages ofpipeline isdone insuchawaythatpipeline canbeclocked athighfrequency. Control andforward of'data flow' amongthestages aretaken careby dedicated hardwarelogic. Different blocksofthe execution unitanddependency amongthemselves areexplained indetails withthehelpofrelevant blockdiagrams. Thedesign hasbeenmodeled inverilog HDL andfunctional verification policies adoptedforithavebeendescribed thoroughly. Synthesis ofthedesign iscarried outat0.13-micron standard celltechnology andforslowtiminglibrary thereported frequency ofoperation is714MHz atsynthesis level. IndexTeriMU, Pipeline, Dependency Resolver, Register File, RISCprocessor
10 citations
01 Sep 2006
TL;DR: In this article, the architecture and design of the pipelined execution unit of a 32-bit RISC processor are described in detail in verilog HDL and functional verification policies adopted for it have been described thoroughly.
Abstract: The paper describes the architecture and design of the pipelined execution unit of a 32-bit RISC processor. Organization of the blocks in different stages of pipeline is done in such a way that pipeline can be clocked at high frequency. Control and forward of `data flow' among the stages are taken care by dedicated hardware logic. Different blocks of the execution unit and dependency among themselves are explained in details with the help of relevant block diagrams. The design has been modeled in verilog HDL and functional verification policies adopted for it have been described thoroughly. Synthesis of the design is carried out at 0.13-micron standard cell technology and for slow timing library the reported frequency of operation is 714 MHz at synthesis level.
8 citations
26 Feb 2015
TL;DR: The aim of the work is to design and reduce the power consumption of low power 32 bits RISC core processor based on 5-stage pipelined DLX architecture using HDL modification technique.
Abstract: The aim of the work is to design and reduce the power consumption of low power 32 bits RISC core processor. The design is based on 5-stage pipelined DLX architecture. This paper proposes the design for the low power RISC processor. The DLX architecture with pipelined control in a RISC core consists of Fetch, Decode, Execute, Pipeline Control and Memory. The reduction in the power is achieved using HDL modification technique. Leakage power i.e Quiescent power which is also a static power in the processor cannot be reduced. Algorithm modification in the execute block of the RISC core will reduce the power consumed by the processor. 13.33% is the total power reduction between a normal processor and the low power version of the processor.
5 citations
"Design and Implementation of Power ..." refers methods in this paper
...Figure 1 shows DLX Architecture as used in [1]....
[...]
...For our study, various papers referred are as given below: ([1])Soumya Murthy, Usha Verma proposed a design to reduce power consumption by including following techniques [1]: a) Only enabling BRAM during active read or write cycles b) Design with Synchronous Resets c) Using Clock Enables...
[...]