Proceedings ArticleDOI
Design and implementation of real time secured RS232 link for multiple FPGA communication
Suman Sau,Chandrajit Pal,Amlan Chakrabarti +2 more
- pp 391-396
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TLDR
The design and implementation of a 32-bit RSA algorithms is demonstrated by developing suitable Hardware and Software design on Xilinx Spartan- 3E (XC3S500E-FG320) device and the implementation has been tested successfully for real time serial data communication between multiple FPGA devices using the RS232 serial interface.Abstract:
Field Programmable Gate Array (FPGA) devices are coming very strongly in the digital hardware systems due to the availability of ready to use resources, parallel logic operations and reconfigurable designs. The usage of FPGA systems in real time domain is also a very fruitful proposition as the FPGA devices are coming with processing cores for Real Time data processing. In a complex system scenario involving a large amount of processing tasks, there is a requirement of building the system using multiple FPGA devices. To make this possible we have to establish a real time data communication between the FPGA devices and to make it even better we have to apply data encryption techniques for making this communication secured.In this paper we demonstrate the design and implementation of a 32-bit RSA algorithms by developing suitable Hardware and Software design on Xilinx Spartan- 3E (XC3S500E-FG320) device, the implementation has been tested successfully for real time serial data communication between multiple FPGA devices using the RS232 serial interface. This development work is also useful for the embedded applications, which requires on board execution of security algorithms. The system is optimized in terms of execution speed and also has been verified using real time debugging tools.read more
Citations
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Journal Article
High Secured AES Encryption and Decryption Algorithm using Xilinx
Chittiprolu. J S Manikanta Nitish,Polepalli. Mani Sai Susmitha,Vakapalli. Steven Viswash,Chandu. Uday Kishore,Ch. Srigiri +4 more
TL;DR: This project uses Xilinx ISE 14.7i that is associate microcircuit development platform supported the Xilxin ISE 13.3i tool and tends to customize the planning of AES formula to implement merely onXilinx software package to facilitate the developers to change and use the software package simply with none issues throughout installation of style.
Proceedings ArticleDOI
Design and implementation of interfacing two FPGAs
TL;DR: A dice game is proposed as an application to show how two FPGAs can send and receive data to each other in full duplex direction and whoever gets the larger number wins the game.
Book ChapterDOI
Hybrid Cryptosystem’s Design with AES and SHA-1 Algorithms
TL;DR: In this article , the security is given to the information by executing both AES and SHA calculations using Verilog and the plan of AES calculation is tweaked to execute just on Xilinx programming.
Journal Article
Implementation of High Speed Secure Communication Between Multiple FPGA Systems Using RTOS
TL;DR: This project is going to implement cryptographic algorithm utilizing threads run by an RTOS on FPGA systems, and the major issue is that two threads running separately on each board can communicate with each other via RS232 communication link.
References
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TL;DR: An encryption method is presented with the novel property that publicly revealing an encryption key does not thereby reveal the corresponding decryption key.
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A Scalable Architecture for Montgomery Multiplication
TL;DR: The general view of the new architecture is described, hardware organization for its parallel computation is analyzed, and design tradeoffs which are useful to identify the best hardware configuration are discussed.
Book ChapterDOI
High-Radix Design of a Scalable Modular Multiplier
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