Design and implementation of single precision pipelined floating point co-processor
01 Sep 2013-pp 79-82
TL;DR: This paper deals with the comparison of various arithmetic modules and the implementation of optimized floating point ALU and the design is achieved to increase the operating frequency by 1.62 times.
Abstract: Floating point numbers are used in various applications such as medical imaging, radar, telecommunications Etc. This paper deals with the comparison of various arithmetic modules and the implementation of optimized floating point ALU. Here pipelined architecture is used in order to increase the performance and the design is achieved to increase the operating frequency by 1.62 times. The logic is designed using Verilog HDL. Synthesis is done on Encounter by Cadence after timing and logic simulation.
Citations
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01 Nov 2015
TL;DR: The implementation of double precision floating point division algorithm using the Paravartya division technique of ancient Indian Vedic mathematics is proposed and results simulated shows reduction in power consumption and design space when compared to multiple subtractions double precision division method.
Abstract: Divider unit is one of the essential parts of processor design. Usually Divider design is of meticulous interest since the design area utilization is more and divider usage in various applications like cryptography, digital signal Processing, logical computations, encryption and decryption algorithms. Compact and efficient Divider design has always been a challenging task. This paper proposes the implementation of double precision floating point division algorithm using the Paravartya division technique of ancient Indian Vedic mathematics and comparisons are presented with respect to the design of division through multiple subtractions double precision floating point divisor. The division algorithm for double precision floating point division using Verilog Code is introduced and implemented in Artix-7 FPGA series. Results simulated by the proposed algorithm shows reduction in power consumption by 36.63% as well as design space by 29.08% when compared to multiple subtractions double precision division method.
3 citations
01 Dec 2014
TL;DR: A novel architecture of IEEE-754 compatible Floating Point Coprocessor interfaced to an 8- bit microcontroller soft core for distributed array controller ASIC that enables real time floating point computations without the need of 32-bit microcontrollers.
Abstract: This paper describes a novel architecture of IEEE-754 compatible Floating Point Coprocessor (FPC) interfaced to an 8- bit microcontroller soft core for distributed array controller ASIC. FPC supports addition/subtraction, multiplication, division and comparison operations. FPC register bank is mapped as a shared dual port memory with micro-controller to minimize the overhead of data transfer. FPC contains 256×32-bit LUT for storage of trigonometric or user defined functions. LUTs and instruction memory are mapped as “stack” register with microcontroller, so it can be initialized by multiple “push” to a single Special Function Register (SFR). Space borne distributed array controller ASICs utilize 8 bit microcontroller cores due to their advantage in terms of low memory size, area and power consumption, but they are slow in floating point computations. This FPC enables real time floating point computations without the need of 32-bit microcontrollers. The FPC IP core has been implemented in VHDL and its performance has been compared for different cases. Simulation results shows that FPC gives 40× improvement in run time for distributed control applications.
1 citations
Cites methods from "Design and implementation of single..."
...This FPC is interfaced to the 8-bit microcontroller core through ExRAM and SFR interface....
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TL;DR: This article shows the development and implementation of a dedicated processor based on the RISC architecture that allows data processing in floating point format consuming a single clock cycle per instruction.
Abstract: The development of Hardware in the commercial sector is considerably low with respect to the development of Software worldwide, it is worth mentioning that Mexico does not have the appropriate impulse to implement new architectures dedicated to the resolution of specific problems in Hardware for the improvement of processes or analysis of data in an optimal way. Consequently, and in order to improve statistics, this article shows the development and implementation of a dedicated processor based on the RISC architecture that allows data processing in floating point format consuming a single clock cycle per instruction, since it counts with a dedicated Floating Point Unit (UPF) that allows the execution of operations between whole numbers and decimals following the IEEE-754 standard for processing.
1 citations
Cites background from "Design and implementation of single..."
...En la actualidad existen diversos procesadores dedicados desarrollados a nivel académico; por citar dos de ellos se aprecia un proyecto publicado en 2013 a nivel internacional en el congreso “International Conference on Advanced Electronic Systems” (ICAES) desarrollado en la universidad VIT en India [4] el cual presenta un co-procesador con una Unidad Lógica Aritmética de arquitectura segmentada de punto flotante para minimizar la potencia e incrementar la frecuencia de operación con la intención de mejorar el rendimiento del diseño usando Verilog HDL, sin embargo utiliza más de un ciclo de reloj para poder ejecutar las operaciones básicas, mientras que el segundo se trata de un proyecto académico desarrollado en la Escuela Superior de Computo del Instituto Politécnico Nacional [5] donde se implementa un microprocesador en VHDL de 16 bits de arquitectura RISC tipo MIPS con arquitectura Harvard y una Unidad Lógica aritmética simple con esquema de acarreo anticipado por propagación que no permite el procesamiento de datos en punto flotante, no obstante cada instrucción ejecutada se lleva a cabo en un ciclo de reloj....
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Journal Article•
TL;DR: Different Vedic division techniques which can be implemented in IEEE 754 floating point division format are presented to study and compare the effect of various critical parameters in terms of power consumption and area utilization against conventional approaches.
Abstract: Usually the processor arithmetic unit processes arithmetic operations, in that divider design is more critical as it consumes more area and power compared to other arithmetic operations.Efficient and compact Divider design has always been a challenging task. IEEE 754 floating point representations are considered as a computer storage format.This paper presents different Vedic division techniques which can be implemented in IEEE 754 floating point division format and also to study and compare the effect of various critical parameters in terms of power consumption and area utilization against conventional approaches.Vedic methods proven to be encouraging since this allows an easy and efficient way of computing various arithmetic computations. Index Terms IEEE 754, Vedic division. ________________________________________________________________________________________________________
1 citations
Cites background or methods from "Design and implementation of single..."
...When compared to the single precision, double precision the extra bits increases not only the precision but also the range of magnitudes that can be represented [5]....
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...Nikhilam, Paravartya, Dwajanka (direct method or flag method) can be applied for binary division [5]....
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...1 IEEE 754 floating point standard [5]...
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Journal Article•
TL;DR: The design and implementation of single precision floating point co-processor that can be used for statistical analysis is presented and coded in Verilog hardware description language at Register Transfer Level (RTL) and synthesized in virtex 5 device.
Abstract: Floating point arithmetic is widely used in many areas, especially scientific computation and signal processing. The main applications of floating point numbers are in the field of medical imaging, biometrics, motion capture and audio applications.This paper presents the design and implementation of single precision floating point co-processor that can be used for statistical analysis.The design is coded in Verilog hardware description language at Register Transfer Level (RTL) and synthesized in virtex 5 device with the help of Xilinx ISE tool.
References
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Book•
01 Aug 1984
TL;DR: The book highlights modern developments in computer design,I/O and performance and presents real system examples from around the world.
Abstract: From the Publisher:
Always praised for its comprehensive yet accessible treatment and real system examples. The book highlights modern developments in computer design,I/O and performance.
248 citations
"Design and implementation of single..." refers methods in this paper
...[11] By using pipelining multiple operations can be performed simultaneously without changing the execution time of an instruction....
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TL;DR: The design of a component to perform parallel addition of multiple floating-point (FP) operands is explored and the proposed design is more accurate than conventional FP addition using a network of 2-operand FP adders and it may have competitive area and delay depending on the number of input operands.
Abstract: The design of a component to perform parallel addition of multiple floating-point (FP) operands is explored in this work. In particular, a 3-input FP adder is discussed in more detail, but the main concepts and ideas presented in this work are valid for FP adders with more inputs. The proposed design is more accurate than conventional FP addition using a network of 2-operand FP adders and it may have competitive area and delay depending on the number of input operands. Implementation results of a 3-operand FP adder are presented to compare its performance to a network of 2-input FP adders.
35 citations
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TL;DR: An adder/substractor and a multiplier for single precision floating point numbers in IEEE-754 format are presented, suitable for high speed computing, with performance comparable to other available implementations.
Abstract: We present an adder/substractor and a multiplier for single precision floating point numbers in IEEE-754 format. They are fully synthesizable hardware descriptions in VHDL that are available for general and educational use. Each one is presented in a single cycle and pipelined implementation, suitable for high speed computing, with performance comparable to other available implementations. Precision for non-denormal multiplications is under ulp and for additions in /spl plusmn/1 LSB.
33 citations
"Design and implementation of single..." refers background in this paper
...[10] For single precision this value is 127 and for double precision this value is 1023....
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21 Mar 2012
TL;DR: The experimental results shows the functional and timing analysis for all the DSP modules carried out using high performance synthesis software from Altera.
Abstract: In this paper, the implementation of DSP modules such as a floating point ALU are presented and designed. The design is based on high performance FPGA “Cyclone II” and implementation is done after functional and timing simulation. The simulation tool used is ModelSim. The tool for synthesis and implementation is Quartus II. The experimental results shows the functional and timing analysis for all the DSP modules carried out using high performance synthesis software from Altera.
29 citations
08 Jun 2009
TL;DR: A brief description is provided of the decimal floating-point support available for Intel® Architecture processors, compliant with the IEEE Standard 754-2008 for Floating-Point Arithmetic.
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16 citations