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Proceedings ArticleDOI

Design and implementation of SoC Wire Codec for space applications

21 Jul 2011-pp 480-485
TL;DR: In this article, the authors proposed a dedicated Network-on-Chip (NoC) approach called System-on Chip (SoC) Wire, which provides guaranteed system qualification with hot-plug ability, high speed point-to-point connection and support of the adaptive macro-pipeline as compared to the Bus Macros.
Abstract: Dynamic Partial Reconfiguration (DPR) permits a particular portion of an FPGA to be reconfigured while the remaining part continues to operate. In order to communicate between static (which is running during the whole application runtime and stores all critical interfaces ) and dynamic regions we propose dedicated Network-on-Chip (NoC) approach called System-on Chip (SoC) Wire. This SoC Wire provides guaranteed system qualification with hot-plug ability, high speed point-to-point connection and support of the adaptive macro-pipeline as compared to the Bus Macros which suffers from more area and power consumptions. In this paper we designed the SoC Wire Codec by using Verilog HDL code. The implementations have been done using XILINX FPGA platform and the functionality of the system is verified using Modelsim simulation and board level ChipScope PRO. The presented SoC Wire Codec design utilizes 13% reduced area and ultimately reducing cost of the design.
References
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Proceedings ArticleDOI
29 Jul 2009
TL;DR: The current available reprogrammable FPGA technologies will be compared and their suitability for a dynamic partial reconfiguration will be outlined, the requirements to achieve a high reliable fault tolerant system will be presented and a framework is proposed.
Abstract: The demand for high-performance on-board processing in space applications drastically increased because of the discrepancy between extreme high data volume and low downlink channel capacity. Furthermore in-flight reconfigurability and dynamic partial reconfiguration enhances space applications with re-programmable hardware and at run-time adaptive functionality. Therefore it is a maintenance and performance improvement. Furthermore it enables mission specific adaptability on demand on board of S/C. Additionally dynamic partial reconfiguration is an improvement in terms of resource utilization and costs. Current space qualified reprogrammable FPGA technologies provide large logic density and have already successfully demonstrated their suitability for space applications. To achieve such an advanced dynamic partial reconfigurable system an appropriate FPGA architecture has to be chosen and the requirements to meet a high reliable system have to be analyzed. In this paper the current available reprogrammable FPGA technologies will be compared and their suitability for a dynamic partial reconfiguration will be outlined. The requirements to achieve a high reliable fault tolerant system will be presented and a framework is proposed.

57 citations

Proceedings ArticleDOI
22 Jun 2008
TL;DR: A reconfigurable system-on-chip (RSoC) architecture is proposed supported by a flexible communication architecture and a newly developed NoC approach, system- on-chip wire (SoCWire) and outline its performance and the applicability for in-flight reconfigured systems.
Abstract: Configurable system-on-chip (SoC) solutions based on state-of-the art FPGA have successfully demonstrated flexibility and reliability for scientific space applications like the Venus Express mission. Future high end payload applications (e.g. Solar Orbiter) demand high-performance on-board processing because of the discrepancy between extreme high data volume and low downlink channel capacity. Furthermore, in-flight reconfiguration ability enhances the system with re-programmable hardware and thus a maintenance potential. To achieve these advanced design goals a reconfigurable system-on-chip (RSoC) architecture is proposed supported by a flexible communication architecture. The flexibility for on-chip communication is covered by a dedicated network-on-chip (NoC) approach. The configurable system-on-chip solution is introduced and the advantages are outlined. Additionally we present our newly developed NoC approach, system-on-chip wire (SoCWire) and outline its performance and the applicability for in-flight reconfigurable systems.

37 citations

Book ChapterDOI
19 Feb 2009
TL;DR: A flexible Network-on-Chip (NoC) is proposed for applications with high reliability, like space missions, and the conditions for SRAM-based FPGA in space are outlined.
Abstract: Individual Data Processing Units (DPUs) are commonly used for operational control and specific data processing of scientific space instruments. These instruments have to be suitable for the harsh space environment in terms of e.g. temperature and radiation. Thus they need to be robust and fault tolerant to achieve an adequate reliability. The Configurable System-on-Chip (SoC) solution based on FPGA has successfully demonstrated flexibility and reliability for scientific space applications like the Venus Express mission. Future space missions demand high-performance on board processing because of the discrepancy of extreme high data volume and low downlink channel capacity. Furthermore, in-flight reconfiguration ability and dynamic reconfigurable modules enhances the system with maintenance potential and at run-time adaptive functionality. To achieve these advanced design goals a flexible Network-on-Chip (NoC) is proposed for applications with high reliability, like space missions. The conditions for SRAM-based FPGA in space are outlined. Additionally, we present our newly developed NoC approach, System-on-Chip Wire (SoCWire) and outline its performance and suitability for robust dynamic reconfigurable systems.

15 citations

Proceedings Article
22 Jun 2009
TL;DR: The Network-on-Chip (NoC) approach System- on-Chip Wire (SoCWire) is presented and its performance and suitability for robust dynamic reconfigurable systems are outlined and a suitable embedded middleware concept is introduced.
Abstract: Dynamic reconfiguration enhances embedded system with at run-time adaptive functionality and is an improvement in terms of resource utilization and system adaptability. SRAM-based FPGAs provides a dynamic reconfigurable platform with high logic density. The requirements for such an embedded high flexible system based on FPGAs are robustness and reliability to prevent operation interrupts or even system failures. The complexity of a dynamic reconfigurable system with adaptive processing module demands high effort for the user. Therefore a high level abstraction of the communication issues is required to support application development by an appropriate middleware. To achieve such a flexible embedded system we present our Network-on-Chip (NoC) approach System-on-Chip Wire (SoCWire) and outline its performance and suitability for robust dynamic reconfigurable systems. Furthermore we introduce a suitable embedded middleware concept to support the system reconfiguration and the software application development process.

2 citations