Design and implementation of test harness for device drivers in SOC on mobile platforms
02 Mar 2015-pp 1-6
TL;DR: This work proposes to develop a test harness for DMA controller and High Speed Synchronous Serial Interface which can be used for stimulating the distinct functionalities of device under test as well as used for behavioral analysis.
Abstract: Modern SOCs are comprised of a wide range of modules, such as microprocessor cores, memories, peripherals, and customized components, relevant to the targeted application. Testing external peripherals is easy, but testing Embedded peripherals in SOC is challenging task. In order to efficiently carry out design verification of peripheral cores, it is necessary to evaluate device under test with functional coverage metrics. The overall process can be divided in to two closely correlated phases mainly module configuration and module operation. The first one configures the peripheral on the different operation modes, the second one is responsible for exciting the whole device and observing its behavior. In the current work, we propose to develop a test harness for DMA controller and High Speed Synchronous Serial Interface. This proposed test harness can be used for stimulating the distinct functionalities of device under test as well as used for behavioral analysis. We have developed test drivers which can be exploited for testing by adding suitable observability features. Experimental results are provided with suitable functional test coverage to evaluate effectiveness of this test harness.
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TL;DR: A novel frame work that uses multiple instances of simulators with physical high-speed serial interfaces to emulate any real time embedded system communication to detect and fix bugs that relates to synchronization issues that otherwise are very hard to find and fix in very complicated systems, such as SDR.
Abstract: Recent years has seen a tremendous increase in processing requirements of present-day embedded system applications. Embedded systems consist of multiple processing elements (PEs) connected to each other using different types of interfaces. Many complicated tasks are accomplished by embedded systems in varied settings, which may introduce errors during inter-processor communication. Testing such systems is tremendously difficult and challenging from testing non-real time systems. A major part of testing real time embedded systems involves ensuring accuracy and timing in synchronous inter-process communication More specifically, the synchronization and inter-processor communication of real-time applications makes testing a challenging task and due to the demand for higher data rate increases, day-by-day, making testing of such systems even more complex. This paper presents a novel frame work that uses multiple instances of simulators with physical high-speed serial interfaces to emulate any real time embedded system communication. The framework presents a testing technique that detects all faults related to synchronization of high-speed synchronous serial interfaces in a systematic manner. The novelty of our approach is to simulate communication across multiple processors in a simulation environment for detecting and localizing bugs. We verify this framework using a case study consisting of an embedded software defined radio (SDR) system. The test results show the applicability of our approach in fixing bugs that relates to synchronization issues that otherwise are very hard to find and fix in very complicated systems, such as SDR.
4 citations
TL;DR: The presented work uses a technique to simulate, create and enhance the knowledge base used as correlation-based error detection that reduces the development time in detecting synchronization-related errors that occur during communication among multiple high-speed serial interfaces in multiprocessor-based real-time embedded systems.
Abstract: The heterogeneity of the multiple processing elements (PEs) is a feature of real-time embedded systems. General-purpose processors and several embedded processors, as well as dedicated high-speed interfaces, are among these elements. Communication between the processors is among the most significant characteristics of developing such complex systems. Furthermore, synchronization is a common issue during interprocessor communication in embedded systems. Debugging and testing such systems is time-consuming, difficult, and laborious, with the majority of the complexities centered on debugging real-time interprocessor communication, such as synchronization in terms of timing and accuracy. While the hardware design features of heterogeneous multiprocessor real-time embedded systems have received a lot of attention, the design and development of software-based solutions still have the potential to be addressed. In particular, software-based testing becomes challenging due to interprocessor communication and the synchronization of real-time applications. A knowledge-based technique that aids in testing high-speed serial interfaces in multiprocessor-based real-time embedded systems is proposed that needs debugging in real time while an application is running. It is becoming much more important to test and validate these interfaces in real time as the demand for high data transmission rates increases. The presented work uses a technique to simulate, create and enhance the knowledge base used as correlation-based error detection that reduces the development time. The proposed technique helps in detecting synchronization-related errors that occur during communication among multiple high-speed serial interfaces. The presented work also lists a series of experiments to validate the effectiveness of the proposed technique. The results show that the presented techniques are effective for error identification in real-time embedded systems.
References
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TL;DR: In this paper, a general graph-theoretic model is developed at the register transfer level which takes the microprocessor organization and the instruction set as parameters and generate tests to detect all the faults in the fault model.
Abstract: The goal of this paper is to develop test generation procedures for testing microprocessors in a user environment. Classical fault detection methods based on the gate and flip-flop level or on the state diagram level description of microprocessors are not suitable for test generation. The problem is further compounded by the availability of a large variety of microprocessors which differ widely in their organization, instruction repertoire, addressing modes, data storage, and manipulation facilities, etc. In this paper, a general graph-theoretic model is developed at the register transfer level. Any microprocessor can be easily modeled using information only about its instruction set and the functions performed. This information is readily available in the user's manual. A fault model is developed on a functional level quite independent of the implementation details. The effects of faults in the fault model are investigated at the level of the graph-theoretic model. Test generation procedures are proposed which take the microprocessor organization and the instruction set as parameters and generate tests to detect all the faults in the fault model. The complexity of the test sequences measured in terms of the number of instructions is given. Our effort in generating tests for a real microprocessor and evaluating their fault coverage is described.
380 citations
"Design and implementation of test h..." refers background in this paper
...Normally these techniques consist of excitation of different functions and resources of the processors [3]....
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TL;DR: The literature is surveyed, and the experiences of verification practitioners are discussed, regarding coverage metrics, regarding software simulation coverage metrics.
Abstract: Software simulation remains the primary means of functional validation for hardware designs. Coverage metrics ensure optimal use of simulation resources, measure the completeness of validation, and direct simulations toward unexplored areas of the design. This article surveys the literature, and discusses the experiences of verification practitioners, regarding coverage metrics.
210 citations
"Design and implementation of test h..." refers methods in this paper
...Similarly, as specified in software testing [13], it is possible to measure capability of set of stimuli using coverage metrics....
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TL;DR: This paper presents a high-level, functional component-oriented, software-based self-testing methodology for embedded processors and validate the effectiveness and efficiency of the proposed methodology by completely applying it on two different processor implementations of a popular RISC instruction set architecture.
Abstract: Embedded processor testing techniques based on the execution of self-test programs have been recently proposed as an effective alternative to classic external tester-based testing and pure hardware built-in self-test (BIST) approaches. Software-based self-testing is a nonintrusive testing approach and provides at-speed testing capability without any hardware or-performance overheads. In this paper, we first present a high-level, functional component-oriented, software-based self-testing methodology for embedded processors. The proposed methodology aims at high structural fault coverage with low test development and test application cost. Then, we validate the effectiveness of the proposed methodology as a low-cost alternative over structural software-based self-testing methodologies based on automatic test pattern generation and pseudorandom testing. Finally, we demonstrate the effectiveness and efficiency of the proposed methodology by completely applying it on two different processor implementations of a popular RISC instruction set architecture including several gate-level implementations.
188 citations
TL;DR: In this article, the development of fault-finding circuits built into ICs which will disclose defects in today's and tomorrow's block-based designs are examined, as well as their application in fault detection.
Abstract: Developments in fault-finding circuits built into ICs which will disclose defects in today's and tomorrow's block-based designs are examined.
122 citations
"Design and implementation of test h..." refers methods in this paper
...Hardware based techniques consist of SCAN chains and BIST insertions [2]....
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29 Mar 2001
TL;DR: A novel test methodology for testing IP cores in SoCs with embedded processor cores that supports at-speed testing for delay faults and stuck-at testing of IP cores implementing full-scan is presented.
Abstract: We present a novel test methodology for testing IP cores in SoCs with embedded processor cores. A test program is run on the processor core that generates and delivers test patterns to the target IP cores in the SoC and analyzes the test responses. This provides tremendous flexibility in the type of patterns that can be applied to the IP cores without incurring significant hardware overhead. We use a bus based SoC simulation model to validate our test methodology. The test methodology involves addition of a test wrapper that can be configured for specific test needs. The methodology supports at-speed testing for delay faults and stuck-at testing of IP cores implementing full-scan.
64 citations
"Design and implementation of test h..." refers background in this paper
...Huang et.al [11] proposed a test methodology for testing IP cores in SOC wherein test programs runs on processor core, which generates test patterns in SOC and analyzes test responses....
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